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Virtex-6FPGAEmbeddedTri-ModeEthernetMACWrapperv1.5GettingStartedGuideUG545March1,2011Virtex-6FPGAEmbeddedTEMACWrapperv1.5“Information,”toyou“ASIS”withnowarrantyofanykind,expressorimplied.XilinxmakesnorepresentationthattheInformation,oranyparticularimplementationthereof,isfreefromanyclaimsofinfringement.YouareresponsibleforobtaininganyrightsyoumayrequireforanyimplementationbasedontheInformation.Allspecificationsaresubjecttochangewithoutnotice.XILINXEXPRESSLYDISCLAIMSANYWARRANTYWHATSOEVERWITHRESPECTTOTHEADEQUACYOFTHEINFORMATIONORANYIMPLEMENTATIONBASEDTHEREON,INCLUDINGBUTNOTLIMITEDTOANYWARRANTIESORREPRESENTATIONSTHATTHISIMPLEMENTATIONISFREEFROMCLAIMSOFINFRINGEMENTANDANYIMPLIEDWARRANTIESOFMERCHANTABILITYORFITNESSFORAPARTICULARPURPOSE.Exceptasstatedherein,noneoftheInformationmaybecopied,reproduced,distributed,republished,downloaded,displayed,posted,ortransmittedinanyformorbyanymeansincluding,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withoutthepriorwrittenconsentofXilinx.©2009-2011Xilinx,Inc.Allrightsreserved.Xilinx,Inc.XILINX,theXilinxlogo,Virtex,Spartan,ISEandotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.Allothertrademarksarethepropertyoftheirrespectiveowners.RevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.DateVersionRevision04/24/091.0InitialXilinxrelease.06/24/091.1Updatedcoretov1.2andISE®tov11.2.AddedVirtex®-6CXTsupport.09/16/092.0Updatedcoretov1.3andISEtov11.3.AddedVirtex-6HXTandVirtex-6-1Lsupport.10/15/092.0.1AddedAppendixE,DebuggingDesigns.04/19/102.1Updatedcoretov1.4andISEtov12.1.03/01/112.2Updatedcoretov1.5andXilinxtoolstov13.1Virtex-6FPGAEmbeddedTEMACWrapperv1.5:AboutThisGuideGuideContents..............................................................9Conventions................................................................10Typographical............................................................10OnlineDocument.........................................................11Chapter1:IntroductionSystemRequirements.......................................................13AbouttheEthernetMACWrapperCore.....................................13DesignsUsingSerialTransceivers...........................................13RecommendedDesignExperience...........................................14AdditionalResources.......................................................14TechnicalSupport...........................................................14Feedback....................................................................14EthernetMACWrapper...................................................14Document...............................................................14Chapter2:LicensingtheCoreBeforeyouBegin............................................................15LicenseOptions.............................................................15ObtainingYourFullLicenseKey............................................15InstallingYourLicenseFile.................................................15Chapter3:QuickStartExampleDesignOverview...................................................................17GeneratingtheEthernetMACWrapper......................................19ImplementingtheExampleDesign..........................................20RunningtheSimulation.....................................................20FunctionalSimulation.....................................................20Virtex-6Devices.......................................................20VHDLSimulation......................................................21VerilogSimulation.....................................................21TimingSimulation........................................................21VHDLSimulation......................................................22VerilogSimulation.....................................................22ExampleDesignDetail......................................................22TableofContents4:CustomizingtheCoreEthernetMACWrapperScreens.............................................23InterfaceConfigurationOptions:Screen1....................................23ComponentName......................................................24PhysicalInterface......................................................24ClientInterface........................................................25HostandManagementInterfaces..........................................25TransmitterandReceiverConfiguration:Screen2.............................27InitialTransmitterConfiguration..........................................28ReceiverConfiguration..................................................28InitialAddressFilterConfiguration