MIPI协议详细介绍

MIPIProtocolIntroductionMIPIDevelopmentTeam2010-9-2WhatisMIPI?MIPIstandsforMobileIndustryProcessorInterfaceMIPIAllianceisacollaborationofmobileindustryleaders.Objectivetopromoteopenstandardsforinterfacestomobileapplicationprocessors.IntendstospeeddeploymentofnewservicestomobileusersbyestablishingSpec.BoardMembersinMIPIAllianceIntel,Motorola,Nokia,NXP,Samsung,ST,TIWhatisMIPI?MIPIAllianceSpecificationfordisplayDCS(DisplayCommandSet)•DCSisastandardizedcommandsetintendedforcommandmodedisplaymodules.DBI,DPI(DisplayBusInterface,DisplayPixelInterface)•DBI：Parallelinterfacestodisplaymoduleshavingdisplaycontrollersandframebuffers.•DPI：Parallelinterfacestodisplaymoduleswithouton-paneldisplaycontrollerorframebuffer.DSI,CSI(DisplaySerialInterface,CameraSerialInterface)•DSIspecifiesahigh-speedserialinterfacebetweenahostprocessoranddisplaymodule.•CSIspecifiesahigh-speedserialinterfacebetweenahostprocessorandcameramodule.D-PHY•D-PHYprovidesthephysicallayerdefinitionforDSIandCSI.DSILayersDCSspecDSIspecD-PHYspecOutlineD-PHYIntroductionLaneModule,StateandLinelevelsOperatingModes•EscapeModeSystemPowerStatesElectricalCharacteristicsSummaryIntroductionforD-PHYD-PHYdescribesasourcesynchronous,highspeed,lowpower,lowcostPHYAPHYconfigurationcontainsAClockLaneOneormoreDataLanesThreemainlanetypesUnidirectionalClockLaneUnidirectionalDataLaneBi-directionalDataLaneTransmissionModeLow-Powersignalingmodeforcontrolpurpose：10MHz(max)High-Speedsignalingmodeforfast-datatraffic：80Mbps~1GbpsperLaneD-PHYlow-levelprotocolspecifiesaminimumdataunitofonebyteAtransmittershallsenddataLSBfirst,MSBlast.D-PHYsuitedformobileapplicationsDSI：DisplaySerialInterface•Aclocklane,Onetofourdatalanes.CSI：CameraSerialInterfaceTwoDataLanePHYConfigurationLaneModulePHYconsistsofD-PHY(LaneModule)D-PHYmaycontainLow-PowerTransmitter(LP-TX)Low-PowerReceiver(LP-RX)High-SpeedTransmitter(HS-TX)High-SpeedReceiver(HS-RX)Low-PowerContentionDetector(LP-CD)ThreemainlanetypesUnidirectionalClockLane•Master：HS-TX,LP-TX•Slave：HS-RX,LP-RXUnidirectionalDataLane•Master：HS-TX,LP-TX•Slave：HS-RX,LP-RXBi-directionalDataLaneMaster,Slave：HS-TX,HS-RX,LP-TX,LP-RX,LP-CDUniversalLaneModuleArchitectureLaneStatesandLineLevelsThetwoLP-TX’sdrivethetwoLinesofaLaneindependentlyandsingle-ended.•FourpossibleLow-PowerLanestates(LP-00,LP-01,LP-10,LP-11)AHS-TXdrivestheLanedifferentially.•TwopossibleHighSpeedLanestates(HS-0,HS-1)DuringHStransmissiontheLPReceiversobserveLP-00ontheLinesLineLevels(typical)•LP：0~1.2V•HS：100~300mV(Swing：200mV)LaneStates•LP-00,LP-01,LP-10,LP-11•HS-0,HS-1OperatingModesTherearethreeoperatingmodesinDataLane•Escapemode,High-Speed(Burst)modeandControlmodePossibleeventsstartingfromtheStopStateofcontrolmode•Escapemoderequest(LP-11→LP-10→LP-00→LP-01→LP-00)•High-Speedmoderequest(LP-11→LP-01→LP-00)•Turnaroundrequest(LP-11→LP-10→LP-00→LP-10→LP-00)EscapeModeEscapemodeisaspecialoperationforDataLanesusingLPstates.Withthismodesomeadditionalfunctionalitybecomesavailable：LPDT,ULPS,TriggerADataLaneshallenterEscapemodeviaLP-11→LP-10→LP-00→LP-01→LP-00OnceEscapemodeisentered,thetransmittershallsendan8-bitentrycommandtoindicatetherequestedaction.EscapemodeusesSpaced-One-HotEncoding.meanseachMarkStateisinterleavedwithaSpaceState(LP-00).SendMark-0/1followedbyaSpacetotransmita‘zero-bit’/‘one-bit’ADataLaneshallexitEscapemodeviaLP-10→LP-11Ultra-LowPowerStateDuringthisstate,theLinesareintheSpacestate(LP-00)ExitedbymeansofaMark-1statewithalengthTWAKEUP(1ms)followedbyaStopstate.EscapeModeClockLaneUltra-LowPowerStateAClockLaneshallenterULPSviaLP-11→LP-10→LP-00exitedbymeansofaMark-1withalengthTWAKEUPfollowedbyaStopStateLP-10→TWAKEUP→LP-11TheminimumvalueofTWAKEUPis1msHigh-SpeedDataTransmissionTheactionofsendinghigh-speedserialdataiscalledHStransmissionorburst.Start-of-TransmissionLP-11→LP-01→LP-00→SoT(0001_1101)HSDataTransmissionBurstAllLaneswillstartsynchronouslyButmayendatdifferenttimesTheclockLaneshallbeinHigh-Speedmode,providingaDDRClocktotheSlavesideEnd-of-TransmissionHTogglesdifferentialstateimmediatelyafterlastpayloaddatabitandkeepsthatstateforatimeTHS-TRAILHigh-SpeedClockTransmissionSwitchingtheClockLanebetweenClockTransmissionandLPModeAClockLaneisaunidirectionalLanefromMastertoSlaveInHSmode,theclockLaneprovidesalow-swing,differentialDDRclocksignal.theClockBurstalwaysstartsandendswithanHS-0state.theClockBurstalwayscontainsanevennumberoftransitionsSummaryforD-PHYLaneModule,LaneStateandLineLevelsLaneModule：LP-TX,LP-RX,HS-TX,HS-RX,LP-CDLaneStates：LP-00,LP-01,LP-10,LP-11,HS-0,HS-1LineLevels(typical)：LP：0~1.2V,HS：100~300mV(Swing：200mV)OperatingModesEscapeModeentryprocedure：LP-11→LP-10→LP-00→LP-01→LP-00→EntryCode→LPD(10MHz)EscapeModeexitprocedure：LP-10→LP-11HighSpeedModeentryprocedure：LP-11→LP-01→LP-00→SoT(00011101)→HSD(80Mbps~1Gbps)HighSpeedModeexitprocedure：EoT→LP-11ControlMode-BTAtransmissionprocedure：LP-11→LP-10→LP-00→LP-10→LP-00ControlMode-BTAreceiveprocedure：LP-00→LP-10→LP-11SystemPowerStatesLow-Powermode,Hig