任意分频Verilog实现

1.2NNN0N-1012.2N+11X/(2N+1)2N1-X/2N+12N102N-1X(00X2N025015011502^_^3.N-0.5N0N-1N-0.50.5CLKN0CLKN-0.5N-0.5N=33NA/BNABZABNN1NaNaN+1B-aNBAaB-A;N1A.72/5a37382:always@(posedgeclkorposedgereset)if(reset)begink=0;clk_10=0;endelseif(k==4)begink=0;clk_10=~clk_10;endelsek=k+1;always@(negedgeclk)clk_2=~clk_2;11always@(posedgeclk)if(!reset)begini=0;clk11=0;endelseif(i==5)beginclk11=~clk11;i=i+1;endelseif(i==10)begini=0;clk11=~clk11;endelsei=i+1;alwaysalways@(posedgeclk)if(!reset)i=0;elsebeginif(i==10)i=0;elsei=i+1;endalways@(posedgeclk)if(!reset)clk11=0;elseif((i==5)|(i==10))clk11=~clk11;alwaysalways@(posedgeclkornegedgeclk)if(reset)begink=0;clk_11=0;endelseif(k==10)begink=0;clk_11=~clk_11;endelsek=k+1;1.21212132311515505050NN(N-1)250nN(N-1)250n50n50n211332n+0.5nn-1100n-11n-1n+0.5n-1n-1n-1n-10n+0.5452.5FPGA3D6310.1910111F=(910+111)(9+1)=10.1N-0.5(N)NN-132n-150cnt(2n-1)1cnt02cnt=n122n-1)/22n-1)2clkout2n-15077S2cnt4verilogmodulefdiv(clk,reset_n,clkout);inputclk;inputreset_n;outputclkout;reg[1:0]count;regdiv1;regdiv2;always@(posedgeclk)beginif(reset_n)count=2'b00;elsecase(count)2'b00:count=2'b01;2'b01:count=2'b10;2'b10:count=2'b00;default:count=2'b00;endcaseendalways@(posedgereset_norposedgeclk)beginif(reset_n)div1=1'b1;elseif(count==2'b00)div1=~div1;endalways@(posedgereset_nornegedgeclk)beginif(reset_n)div2=1'b1;elseif(count==2'b10)div2=~div2;endassignclkout=div1^div2;endmodule