IEEE P13641

RecognizedasanIEEEP1364.1-2001AmericanNationalStandardJune15,2001TheInstituteofElectricalandElectronicsEngineers,Inc.345East47thStreet,NewYork,NY10017-2394,USACopyright©2001bytheInstituteofElectricalandElectronicsEngineers,Inc.Allrightsreserved.Published2001.PrintedintheUnitedStatesofAmericaISBNXXXXXXXXXXNopartofthispublicationmaybereproducedinanyform,inanelectronicretrievalsystemorotherwise,withoutthepriorwrittenpermissionofthepublisher.IEEEP1364.1/D1.6DraftStandardforVerilog®RegisterTransferLevelSynthesisPreparedbytheVerilogSynthesisInteroperabilityWorkingGroupoftheDesignAutomationStandardsCommitteeSponsorDesig[e-mail]andardsDraft,subjecttochange.IEEEStandardsdocumentsaredevelopedwithintheTechnicalCommitteesoftheIEEESocietiesandtheStandardsCoordinatingCommitteesoftheIEEEStandardsBoard.Membersofthecommitteesservevolun-tarilyandwithoutcompensation.TheyarenotnecessarilymembersoftheInstitute.ThestandardsdevelopedwithinIEEErepresentaconsensusofthebroadexpertiseonthesubjectwithintheInstituteaswellasthoseactivitiesoutsideofIEEEthathaveexpressedaninterestinparticipatinginthedevelopmentofthestandard.UseofanIEEEStandardiswhollyvoluntary.TheexistenceofanIEEEStandarddoesnotimplythattherearenootherwaystoproduce,test,measure,purchase,market,orprovideothergoodsandservicesrelatedtothescopeoftheIEEEStandard.Furthermore,theviewpointexpressedatthetimeastandardisapprovedandissuedissubjecttochangebroughtaboutthroughdevelopmentsinthestateoftheartandcommentsreceivedfromusersofthestandard.EveryIEEEStandardissubjectedtoreviewatleasteveryfiveyearsforrevisionorreaffirmation.Whenadocumentismorethanfiveyearsoldandhasnotbeenreaffirmed,itisrea-sonabletoconcludethatitscontents,althoughstillofsomevalue,donotwhollyreflectthepresentstateoftheart.UsersarecautionedtochecktodeterminethattheyhavethelatesteditionofanyIEEEStandard.CommentsforrevisionofIEEEStandardsarewelcomefromanyinterestedparty,regardlessofmembershipaffiliationwithIEEE.Suggestionsforchangesindocumentsshouldbeintheformofaproposedchangeoftext,togetherwithappropriatesupportingcomments.Interpretations:Occasionallyquestionsmayariseregardingthemeaningofportionsofstandardsastheyrelatetospecificapplications.WhentheneedforinterpretationsisbroughttotheattentionofIEEE,theInstitutewillinitiateactiontoprepareappropriateresponses.SinceIEEEStandardsrepresentaconsensusofallconcernedinterests,itisimportanttoensurethatanyinterpretationhasalsoreceivedtheconcurrenceofabalanceofinterests.ForthisreasonIEEEandthemembersofitstechnicalcommitteesarenotabletopro-videaninstantresponsetointerpretationrequestsexceptinthosecaseswherethematterhaspreviouslyreceivedformalconsideration.Commentsonstandardsandrequestsforinterpretationsshouldbeaddressedto:Secretary,IEEEStandardsBoard445HoesLaneP.O.Box1331Piscataway,NJ08855-1331USAAuthorizationtophotocopyportionsofanyindividualstandardforinternalorpersonaluseisgrantedbytheInstituteofElectricalandElectronicsEngineers,Inc.,providedthattheappropriatefeeispaidtoCopyrightClearanceCenter.Toarrangeforpaymentoflicensingfee,pleasecontactCopyrightClearanceCenter,Cus-tomerService,222RosewoodDrive,Danvers,MA01923USA;[phone].PermissiontophotocopyportionsofanyindividualstandardforeducationalclassroomusecanalsobeobtainedthroughtheCopy-rightClearanceCenter.Note:Attentioniscalledtothepossibilitythatimplementationofthisstandardmayrequireuseofsubjectmattercoveredbypatentrights.Bypublicationofthisstandard,nopositionistakenwithrespecttotheexistenceorvalidityofanypatentrightsinconnectiontherewith.TheIEEEshallnotberesponsibleforidentifyingallpatentsforwhichalicensemayberequiredbyanIEEEstandardorforconductinginquiriesintothelegalval[e-mail]EStandardsDraft,subjecttochange.Introduction(ThisintroductionisnotapartofIEEEP1364.1,DraftStandardRegisterTransferLevelSubsetBasedontheVerilog®HardwareDescriptionLanguage.)ThisstandarddescribesastandardsyntaxandsemanticsforVerilogHDLbasedRTLsynthesis.ItdefinesthesubsetofIEEE1364-2001(VerilogHDL)thatissuitableforRTLsynthesisanddefinesthesemanticsofthatsubsetforthesynthesisdomain.ThepurposeofthisstandardistodefineasyntaxandsemanticsthatcanbeusedincommonbyallcompliantRTLsynthesistoolstoachieveuniformityofresultsinasimilarmannertowhichsimulationandanalysistoolsusetheIEEE1364standard.Thiswillallowusersofsynthesistoolstoproducewelldefineddesignswhosefunctionalcharacteristicsareindependentofaparticularsynthesisimplementationbymakingtheirdesignscompliantwiththisstandard.Thestandardisintendedforusebylogicdesignersandelectronicengineers.InitialworkonthisstandardstartedasaRTLsynthesissubsetworkinggroupunderOpenVerilogInterna-tional(OVI).AfterOVIapprovedofthedraft1.0withanoverwhelmingaffirmativeresponse,anIEEEPARwasobtainedtoclearitswayforIEEEstandardization.MostofthemembersoftheoriginalgroupcontinuedtobepartofthePilotGroupunderP1364.1toleadthetechnicalwork.T