基于FPGA的IEEE1394物理层模块设计与实现

华中科技大学硕士学位论文基于FPGA的IEEE1394物理层模块设计与实现姓名：龙翔林申请学位级别：硕士专业：模式识别与智能系统指导教师：汪国有20060510ILS-1394IEEE1394FPGA100MbpsIEEE1394IEEE1394IEEE1394NRZISALS-1394TITSB41AB23PCI-139413941394,IEEE13941995IEEE1394IEEE13941394;;FPGAIIAbstractThisprojectcomesfromproject“DesignofLs-1394Controller”supportedbyXi’anmicro-electronicinstitution,aimingtodesignthe1394ASICworkedinthecablemodewithourownnationalintellectualproperties.The1394ASIChastwomodulesthatintegratedinonechip,oneisLLCmoduledesignedbyMaRongyiandtheotheristri-interfacePHYmodulewhichproposedinthisarticle.Thearticlefirstanalysesthe1394PHYlayerprotocolanddescribestherequirementofthePHYlayersindetails.Afterthat,thisarticleanalysestherequirementofthecontroller,andmakesaplanofmainstructure:includingcircuitdiagram,choiceoftheFPGAandmoduleofthecontroller.Then,thearticleexpandsPHYlayerdesign,analysesthedesignofPHYlayersub-modulesthoroughlyanddividesitintothreesub-modules,whicharecableinterface,datatransceiverandLLCinterface.First,thearticledescribestheprocessofhowtoimplementthebusconfiguration,busarbitrationanddatatransceiverfromtheinterfacesignalchanges,bydecomposingthemainmachinestateincableinterface.Andthenitanalysesthedatatransceiversub-moduleindetail.Thedatatransceiversub-moduleprocessesreceiveddatasynchronization,datatransmittingorre-transmitting,anddataencoding.Atlast,LLCinterfacesub-moduleexplainsthedataexchangemodeofPHYlayerandLLClayerbysolvingtheproblemofhowtouploadthereceiveddata,processtherequestoftheLLCinterface,sendthedataofLLClayerandcreatetheself_IDpacketetc.Atlast,thearticledescribesthedesignofthetestingprocessandthewholeperformanceoftheprojectbyconnectingwiththePCI1394cardwhichbasedontheTSB41AB23ofTI.Inordertomakethedesigncompatibletotheprotocol,wetestthebasictransmitting,communicationofmegadataandtheconnectionexperimentbetweenIIIthem.Afterintroducingtheconstructionoftheverificationsystemandtheverificationmethod,thearticlesuggeststhebestwaytoresolvethequestionssuchashowtodesignthefunctionmoduleandhowtofindthebestFPGA.ThesystemtestresultindicatesthatthecontrollerdesignproposedaboveiscompletelycompatibletotheIEEE13941995standard,andcanformanintegratedIEEE1394nodecontrollerbycombiningwiththeIEEE1394LLCmodule.KeywordsIEEE1394;PHYModule;FPGA111.1AppleIEEE1394FireWireSonyTexasInstrumentsSonyi.LinkTILynxIEEE1995FireWireIEEE1394-1995IEEE1394aIEEE1394b400Mbps3.2GbpsIEEE139419951394IEEE1394OSIOpenSystemsInterconnection/1.1IEEE139421.2CycloneFPGAIEEE-1394ISA13941394Ti1394PCIPCFPGAIEEE-1394CycloneFPGAISA-13941)IEEEstd1394-19952)LLC(LinkLayerContoller)32bit3)PHY(PhyscialLayerContoller)100Mbps13944)1394IEEEstd1394-1995Ti1394PCI5)ISA-1394ISA1394ISAPCISAISA16bit/8bit8bitISALLC32bitISAInt()WindriverWindriverISA1394ISAISAISA313941394FPGAFPGA139432bit1.31)1.2Based-ISA1394ISACPLDEPM7256AETC144ISAFPGAEP1C12Q240C8LLCPHY32bit139411394213943FPGA42)IEEE139413943)IEEE13944)IEEE139452IEEE1394IEEE13941394139413941394TOP13942.1IEEE13942.1.113943139413946222.113941VP840Vdc2VG13943TPB+4TPB-TPBSTRB5TPA+6TPA-TPADATA301ZZZ”TPATPB1394TPA(TPB)TPB(TPA)TPA+TPB+TPA-TPB-62.1.2FPGASCLKPhyLlcCtrl[1..0]PhyLlcData[1..0]LlcPhyCtrl[1..0]LlcPhyData[1..0]LREQ24.576MHz98.304M4SCLK49.152M2bitPhyLlcCtrl[1..0]LlcPhyCtrl[1..0]1394LREQLREQ10bit2.22.2.11394TPATPB1394TOP2.2.213941)1394IEEE1394167uS2)713943)100MbpsIDLE8DATA_PREFIXGRANTDATA_ENDIDENT_DONE2.2.311394ImmReqPriReqFairReqIsoReqImmReq231394TPATPBStrbDataStrbData(NRZ)StrbStrbStrbDataNRZStrbData4IEEE1394125uS92.32.3.1LREQ34ImmReqIsoReqFairReqPriReqLREQbitbit2.22.2bit0bit1~3bit4~6bit71000ImmReq001IsoReq010PriReq011FairReq100Mbps0bit0bit1~3bit4~7bit811000bit0bit1~3bit4~7bit8~15bit16110102.3.210PhyLlcCtrl[1..0]LlcPhyCtrl[1..0]2.32.3PhyLlcCtrl[1..0]00011011LlcPhyCtrl[1..0]00011011113IEEE1394IEEE13943.13.1.1139462.113943.1100Mbps13943.1.23.1TPAStrbDataTPBDataStrb3.1100Mbps139412TPA1.86VTPB0.8V3.13.111001110013943.23.2.1SN65LVDS3487TI4TISN65LVDS3486B4Vid-32mV1Vid-100mV0Vid0V17SN65LVDS3486B3.2.2FPGAFPGAI/O1I/O139432(Data[31..0])8(Addr[7..0])6(Reset,Int,Wr,Cs,Ack,Bclk)46I/O134Arb_A[1..0],Arb_B[1..0]2Strb_Rx,Data_Rx2(Strb_Tx,Data_Tx2(Strb_En,Data_En1(Port_Status)1(Led)12I/O336I/OI/O8226000FIFO100Mbps512105KRAM31394100MbpsFPGA100MHz1/41/3100M2bit50M200MHzFPGAFPGA4FPGAEP1C12Q240C8AlteraCyclone169I/O12060239616RAM275MHz8nS3.33FIFO3.2143.3.11)3.1A_Rx0[1..0]0TPAB_Rx0[1..0]0TPBA_Rx1[1..0]1TPAB_Rx1[1..0]1TPBA_Rx2[1..0]2TPAB_Rx2[1..0]2TPBPortStatus00PortStatus11PortStatus22102)FIFO3.2153.2RootHoldINInitBusRstINGapCnt[5..0]INImmReqINIsoReqINPriReqINFairReqINTransFinishedINRootFlagOUTNodeNotify[11..0]OUTPortUseStatus[5..0]OUTBusEvent[3..0]OUTRecvPort[1..0]OUTSelfIdReceiveingFlagOUTSelfIdTransmitingFlagOUTReceiveingFlagOUTTransmitingFlagOUTNodeNotify[11..0]33.3.21)3.3DataRx00StrbRx00StrbDataRx11StrbRx11StrbDataRx22StrbRx22StrbStrbData0[1..0]0StrbDataStrbData1[1..0]1StrbDataStrbData2[1..0]2StrbDataPortEnable0[1..0]0StrbDataPortEnable1[1..0]1StrbDataPortEnable2[1..0]2StrbData162)3.4NodeNotify[11..0]INRecvPort[1..0]INTransData[1..0]INSelfIdReceiveingFlagINSelfIdTransmitingFlagINRec