现代CMOS工艺基本流程

1现代CMOS工艺基本流程现代CMOS工艺基本流程2SiliconSubstrateP+~2um~725umSiliconEpiLayerP−选择衬底•晶圆的选择–掺杂类型（N或P）–电阻率（掺杂浓度）–晶向•高掺杂(P+)的Si晶圆•低掺杂(P−)的Si外延层3SiliconSubstrateP+SiliconEpiLayerP−PadOxide热氧化•热氧化–形成一个SiO2薄层，厚度约20nm–高温，H2O或O2气氛–缓解后续步骤形成的Si3N4对Si衬底造成的应力4SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideSi3N4淀积•Si3N4淀积–厚度约250nm–化学气相淀积(CVD)–作为后续CMP的停止层5SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresist光刻胶成形•光刻胶成形–厚度约0.5~1.0um–光刻胶涂敷、曝光和显影–用于隔离浅槽的定义6SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresistSi3N4和SiO2刻蚀•Si3N4和SiO2刻蚀–基于氟的反应离子刻蚀(RIE)7SiliconSubstrateP+SiliconEpiLayerP-SiliconNitridePhotoresistTransistorActiveAreasIsolationTrenches隔离浅槽刻蚀•隔离浅槽刻蚀–基于氟的反应离子刻蚀(RIE)–定义晶体管有源区8SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideTransistorActiveAreasIsolationTrenches除去光刻胶•除去光刻胶–氧等离子体去胶，把光刻胶成分氧化为气体9SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideFuturePMOSTransistorSiliconDioxideFutureNMOSTransistorNocurrentcanflowthroughhere!SiO2淀积•SiO2淀积–用氧化物填充隔离浅槽–厚度约为0.5~1.0um，和浅槽深度和几何形状有关–化学气相淀积(CVD)10SiliconSubstrateP+SiliconEpiLayerP-SiliconNitrideFuturePMOSTransistorFutureNMOSTransistorNocurrentcanflowthroughhere!化学机械抛光•化学机械抛光(CMP)–CMP除去表面的氧化层–到Si3N4层为止11SiliconSubstrateP+SiliconEpiLayerP-FuturePMOSTransistorFutureNMOSTransistor除去Si3N4•除去Si3N4–热磷酸(H3PO4)湿法刻蚀，约180℃12TrenchOxideCrossSectionBareSilicon平面视图•完成浅槽隔离(STI)13SiliconSubstrateP+SiliconEpiLayerP-FuturePMOSTransistorFutureNMOSTransistorPhotoresist光刻胶成形•光刻胶成形–厚度比较厚，用于阻挡离子注入–用于N-阱的定义14SiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorPhotoresistN-WellPhosphorous(-)Ions磷离子注入•磷离子注入–高能磷离子注入–形成局部N型区域，用于制造PMOS管15SiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorN-Well除去光刻胶16PhotoresistSiliconSubstrateP+SiliconEpiLayerP-FutureNMOSTransistorN-Well光刻胶成形•光刻胶成形–厚度比较厚，用于阻挡离子注入–用于P-阱的定义17SiliconSubstrateP+SiliconEpiLayerP-PhotoresistN-WellBoron(+)IonsP-Well•硼离子注入–高能硼离子注入–形成局部P型区域，用于制造NMOS管硼离子注入18SiliconSubstrateP+SiliconEpiLayerP-N-WellP-Well除去光刻胶19SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Well退火•退火–在600~1000℃的H2环境中加热–修复离子注入造成的Si表面晶体损伤–注入杂质的电激活–同时会造成杂质的进一步扩散–快速加热工艺(RTP)可以减少杂质的扩散20TrenchOxideN-WellP-WellCrossSection•完成N-阱和P-阱平面视图21SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSacrificialOxide牺牲氧化层生长•牺牲氧化层生长–厚度约25nm–用来捕获Si表面的缺陷22SiliconSubstrateP+SiliconEpiLayerP-P-WellN-Well除去牺牲氧化层•除去牺牲氧化层–HF溶液湿法刻蚀–剩下洁净的Si表面23SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxide栅氧化层生长•栅氧化层生长–工艺中最关键的一步–厚度2~10nm–要求非常洁净，厚度精确(±1Å)–用作晶体管的栅绝缘层24SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPolysilicon多晶硅淀积•多晶硅淀积–厚度150~300nm–化学气相淀积(CVD)25SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistChannelLengthPolysilicon光刻胶成形•光刻胶成形–工艺中最关键的图形转移步骤–栅长的精确性是晶体管开关速度的首要决定因素–使用最先进的曝光技术——深紫外光(DUV)–光刻胶厚度比其他步骤薄26SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistChannelLength多晶硅刻蚀•多晶硅刻蚀–基于氟的反应离子刻蚀(RIE)–必须精确的从光刻胶得到多晶硅的形状27SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxidePolyGateElectrode除去光刻胶28TrenchOxideN-WellP-WellCrossSectionPolysilicon平面视图•完成栅极29SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellGateOxidePolyGateElectrodePolyRe-oxidation多晶硅氧化•多晶硅氧化–在多晶硅表面生长薄氧化层–用于缓冲隔离多晶硅和后续步骤形成的Si3N430SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresist光刻胶成形•光刻胶成形–用于控制NMOS管的衔接注入31SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistArsenic(-)IonsNTipNMOS管衔接注入•NMOS管衔接注入–低能量、浅深度、低掺杂的砷离子注入–衔接注入用于削弱栅区的热载流子效应32SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellNTip除去光刻胶33SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistNTip光刻胶成形•光刻胶成形–用于控制PMOS管的衔接注入34SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistBF2(+)IonsNTipPTip•PMOS管衔接注入–低能量、浅深度、低掺杂的BF2+离子注入–衔接注入用于削弱栅区的热载流子效应PMOS管衔接注入35SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellNTipPTip除去光刻胶36SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSiliconNitrideThinnerHereThickerHereNTipPTipPTipSi3N4淀积•Si3N4淀积–厚度120～180nm–CVD37SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellSpacerSidewallNTipPTipPTipSi3N4刻蚀•Si3N4刻蚀–水平表面的薄层Si3N4被刻蚀，留下隔离侧墙–侧墙精确定位晶体管源区和漏区的离子注入–RIE38SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistNTipPTip光刻胶成形•光刻胶成形–用于控制NMOS管的源/漏区注入39SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellPhotoresistArsenic(-)IonsN+DrainN+SourcePTipNMOS管源/漏注入•NMOS管源/漏注入–浅深度、重掺杂的砷离子注入，形成了重掺杂的源/漏区–隔离侧墙阻挡了栅区附近的注入40SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourcePTip除去光刻胶41SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourcePhotoresistPTip光刻胶成形•光刻胶成形–用于控制PMOS管的源/漏区注入42SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellBF2(+)IonsPhotoresistN+DrainN+SourceP+SourceP+DrainPMOS管源/漏注入•PMOS管源/漏注入–浅深度、重掺杂的BF2+离子注入，形成了重掺杂的源/漏区–隔离侧墙阻挡了栅区附近的注入43SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+SourceP+DrainLightlyDoped“Tips”除去光刻胶和退火•除去光刻胶和退火–用RTP工艺，消除杂质在源/漏区的迁移44TrenchOxidePolysiliconCrossSectionN-WellP-WellN+Source/DrainP+Source/DrainSpacer平面视图•完成晶体管源/漏极，电子器件形成45SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+Source除去表面氧化物•除去表面氧化物–在HF溶液中快速浸泡，使栅、源、漏区的Si暴露出来46SiliconSubstrateP+SiliconEpiLayerP-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumTi淀积•Ti淀积–厚度20~40nm–溅射工艺–Ti淀积在整个晶圆表面47SiliconSubstrateP+SiliconEpiLayerP-P-W