先进芯片封装知识介绍

AdvancedPackagingTechOutline▼PackageDevelopmentTrend▼3DPackage▼WLCSP&FlipChipPackagePackageDevelopmentTrend▼SOFamily▼QFPFamily▼BGAFamilyPackageDevelopmentTrend▼CSPFamily▼MemoryCard▼SiPModulePackageDevelopmentTrend3DPackage3DPackage3DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP3S-CSPS-etCSPetCSP+S-CSPPS-fcCSP+SCSPPoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2PoPQFN4SS-SCSPStackedDieTopdieBottomdieFOWmaterilWireTSV▼TSV(ThroughSiliconVia)Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace.Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips.Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV▼What’sPoP?▲PoPisPackageonPackage▲Topandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.PoPPoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinning▼PoPCoreTechnologyPoP▼Allowsforwarpagereductionbyutilizingfully-moldedstructure▲Morecompatiblewithsubstratethicknessreduction▼Providesfinepitchtoppackageinterfacewiththrumoldvia▼Improvedboardlevelreliability▼Largerdiesize/packagesizeratio▼Compatiblewithflipchip,wirebond,orstackeddieconfigurations▼Costeffectivecomparedtoalternativenextgenerationsolutions▼Amkor’sTMV™PoPTopviewBottomviewThroughMoldViaPoPBallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffect▼ProcessFlowofTMVPoP•Digital(Btmdie)+Analog(Middledie)+Memory(Toppkg)•PotableDigitalGadget–CellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiPEasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:•FilmAdhesivedieattach•EpoxypasteforTopPKG•Auwirebondingforinterconnection•Moldencapsulation▼WhyPiP?PiPMaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControl•TopPackageAttach•DieAttach•etcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISM▼PiPCoreTechnologyPiPMemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiP▼PiP–W/BPiPandFCPiPWLCSP&FlipChipPackageWLCSP•WhatisWLCSP?WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize).WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.WLCSP•WhyWLCSP?–Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.–Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.–Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.–Lowcost:noneedsubstrate,onlyonetimetesting.•WLCSP’sdisadvantage–Becauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).–BecauseoftheRDL,staggerIOisnotallowedforWLCSP.RDL▼RDL:RedistributionLayer▲Aredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).WLCSP•ProcessFlowofWLCSPWLCSP▼ProcessFlowofWLCSPFlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip)BumpBumpDevelopmentBumpDevelopmentBumpDevelopmentC4FlipChip▼What’sC4FlipChip?▼C4is:ControlledCollapsedChipConnection▼ChipisconnectedtosubstratebyRDLandBump▼Bumpmaterialtype:solder,goldC4FlipChipBGA▼MainFeatures▲BallPitch:0.4mm-1.27mm▲Packagesize:upto55mmx55mm▲Substratelayer:4-16Layers▲BallCount:upto2912▲TargetMarket:CPU、FPGA、Processor、Chipset、Memory、Router、Switches、andDSPetc.▼MainBenefits▲ReducedSignalInductance▲ReducedPower/GroundInductance▲HigherSignalDensity▲DieShrink&ReducedPackageFootprint▲HighSpeedandHighthermalsupportC2FlipChip▼What’sC2FlipChip?▲C2is:ChipConnection▲Chipisconnectedtosubstratebycopperpost▲Bumpmaterialtype:copperpostwithsolderplatingSiliconDieCopperpostSolderC2FlipChip▼ProcessFlowofC2C2FlipChip▼Comparison:C2VsC4Insomecases,C2canrepl