MT48LC4M16A2使用说明

164Mb:x4,x8,x16SDRAM64Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.64MSDRAM.p65–Rev.11/99©1999,MicronTechnology,Inc.16Megx48Megx84Megx16Configuration4Megx4x4banks2Megx8x4banks1Megx16x4banksRefreshCount4K4K4KRowAddressing4K(A0-A11)4K(A0-A11)4K(A0-A11)BankAddressing4(BA0,BA1)4(BA0,BA1)4(BA0,BA1)ColumnAddressing1K(A0-A9)512(A0-A8)256(A0-A7)SYNCHRONOUSDRAMMT48LC16M4A2-4Megx4x4banksMT48LC8M8A2-2Megx8x4banksMT48LC4M16A2-1Megx16x4banksForthelatestdatasheet,pleaserefertotheMicronWebsite:(TopView)54-PinTSOPFEATURES•PC66-,PC100-andPC133-compliant•143MHz,graphical4Megx16option•Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock•Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle•Internalbanksforhidingrowaccess/precharge•Programmableburstlengths:1,2,4,8orfullpage•AutoPrecharge,includesCONCURRENTAUTOPRECHARGE,andAutoRefreshModes•SelfRefreshModes:standardandlowpower•64ms,4,096-cyclerefresh•LVTTL-compatibleinputsandoutputs•Single+3.3V±0.3VpowersupplyOPTIONSMARKING•Configurations16Megx4(4Megx4x4banks)16M48Megx8(2Megx8x4banks)8M84Megx16(1Megx16x4banks)4M16•WRITERecovery(tWR)tWR=“2CLK”1A2•PlasticPackage-OCPL254-pinTSOPII(400mil)TG•Timing(CycleTime)10ns@CL2(PC100)-8E7.5ns@CL3(PC133)-757.5ns@CL2(PC133)-7E7ns@CL3(143MHz)-7G3•SelfRefreshStandardNoneLowPowerL•OperatingTemperatureRangeCommercial(0°Cto+70°C)NoneExtended(-40°Cto+85°C)IT4PartNumberExample:MT48LC8M8A2TG-8ENOTE:1.RefertoMicronTechnicalNoteTN-48-05.2.Off-centerpartingline.3.Availableon4Megx16.4.Availableonx8,x16,-8E.VDDDQ0VDDQDQ1DQ2VssQDQ3DQ4VDDQDQ5DQ6VssQDQ7VDDDQMLWE#CAS#RAS#CS#BA0BA1A10A0A1A2A3VDD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928VssDQ15VssQDQ14DQ13VDDQDQ12DQ11VssQDQ10DQ9VDDQDQ8VssNCDQMHCLKCKENCA11A9A8A7A6A5A4Vssx8x16x16x8x4x4-DQ0-NCDQ1-NCDQ2-NCDQ3-NC-NC-------------NC-NCDQ0-NCNC-NCDQ1-NC-NC-------------DQ7-NCDQ6-NCDQ5-NCDQ4-NC--DQM------------NC-NCDQ3-NCNC-NCDQ2-NC--DQM-----------Note:The#symbolindicatessignalisactiveLOW.Adash(–)indicatesx8andx4pinfunctionissameasx16pinfunction.KEYTIMINGPARAMETERSSPEEDCLOCKACCESSTIMESETUPHOLDGRADEFREQUENCYCL=2*CL=3*TIMETIME-7G143MHz–6ns2ns1ns-7E143MHz–5.4ns1.5ns0.8ns-75133MHz–5.4ns1.5ns0.8ns-8E125MHz–6ns2ns1ns-7E133MHz5.4ns–1.5ns0.8ns-75100MHz6ns–1.5ns0.8ns-8E100MHz6ns–2ns1ns*CL=CAS(READ)latency264Mb:x4,x8,x16SDRAM64Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.64MSDRAM.p65–Rev.11/99©1999,MicronTechnology,Inc.commandareusedtoselectthestartingcolumnloca-tionfortheburstaccess.TheSDRAMprovidesforprogrammableREADorWRITEburstlengthsof1,2,4or8locations,orthefullpage,withaburstterminateoption.Anautoprechargefunctionmaybeenabledtoprovideaself-timedrowprechargethatisinitiatedattheendoftheburstsequence.The64MbSDRAMusesaninternalpipelinedarchitecturetoachievehigh-speedoperation.Thisarchitectureiscompatiblewiththe2nruleofprefetcharchitectures,butitalsoallowsthecolumnaddresstobechangedoneveryclockcycletoachieveahigh-speed,fullyrandomaccess.Prechargingonebankwhileaccessingoneoftheotherthreebankswillhidetheprechargecyclesandprovideseamless,high-speed,random-accessoperation.The64MbSDRAMisdesignedtooperatein3.3Vmemorysystems.Anautorefreshmodeisprovided,alongwithapower-saving,power-downmode.AllinputsandoutputsareLVTTL-compatible.SDRAMsoffersubstantialadvancesinDRAMoper-atingperformance,includingtheabilitytosynchro-nouslyburstdataatahighdataratewithautomaticcolumn-addressgeneration,theabilitytointerleavebetweeninternalbanksinordertohideprechargetimeandthecapabilitytorandomlychangecolumnaddressesoneachclockcycleduringaburstaccess.GENERALDESCRIPTIONThe64MbSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontaining67,108,864bits.Itisinternallyconfiguredasaquad-bankDRAMwithasynchronousinterface(allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK).Eachofthex4’s16,777,216-bitbanksisorganizedas4,096rowsby1,024columnsby4bits.Eachofthex8’s16,777,216-bitbanksisorganizedas4,096rowsby512columnsby8bits.Eachofthex16’s16,777,216-bitbanksisorganizedas4,096rowsby256columnsby16bits.ReadandwriteaccessestotheSDRAMareburstoriented;accessesstartataselectedlocationandcon-tinueforaprogrammednumberoflocationsinaprogrammedsequence.AccessesbeginwiththeregistrationofanACTIVEcommand,whichisthenfollowedbyaREADorWRITEcommand.TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobeaccessed(BA0,BA1selectthebank;A0-A11selecttherow).TheaddressbitsregisteredcoincidentwiththeREADorWRITE64MbSDRAMPARTNUMBERSPARTNUMBERARCHITECTUREMT48LC16M4A2TG16Megx4MT48LC8M8A2TG8Megx8MT48LC4M16A2TG4Megx16364Mb:x4,x8,x16SDRAM64Mb:x4,x8,x16SDRAMMicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.64MSDRAM.p65–Rev.11/99©1999,MicronTechnology,Inc.TABLEOFCONTENTSFunctionalBlockDiagram-16Megx4.................4FunctionalBlockDiagram-8Megx8.................5FunctionalBlockDiagram-4Megx16..