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1.1ASYNCHRONOUSINTERFACE–CDCGUIDELINE1.1.1INTRODUCTIONASICdesignisbecomingmorecomplexduetomoreandmoreIPintegratedinachip,anddataisfrequentlytransferredfromoneclockdomaintoanotherdomain.Clockdomaincrossingissuebecomesmoreandmoreimportantvectorinamulti-clock,stableworkchip.Thisdocumentmainlyintroducebelowtopics:a.WherewilloccurCDC;b.WhatproblemwilloccurduetoCDCissue;c.HowtodesignCDClogiccorrectly.1.1.2APPLICATIONAREAInamulti-clockdesign,clockdomaincrossingoccurswheneverdataistransferredfromaflopdrivenbyoneclocktoaflopdrivenbyanotherclock.AsitisshowninFigure1-1,FADQCKFBDQCKCombinationalLogicClockAClockBsignalAsignalBFigure1-1Clockdomaincrossing*Note:definitionofterminology:Sourceclock:ClockAinfigure1-1isdefinedassourceclock;Destinationclock:ClockBinfigure1-1isdefinedasdestinationclock;Sourceclockdomain:AllthelogicdesignwhosereferenceclockisClockA,likeflip-flopFAinfigure1-1;Destinationclockdomain:AllthelogicdesignwhosereferenceclockisClockB,likeflip-flopFBinfigure1-1;1.1.3PROBLEMDEFINITIONMeta-stability,glitch,multi-fanoutandre-convergencemayoccurinanasynchronousdesign,theymaycausedesignenteringanun-anticipantstateandresultinfunctionerror.1.1.3.1Meta-stabilitySignalpropagatecrossasynchronousdomainsmaycreatemeta-stabilityifsetuporholdtimeviolationoccurred,shownasfigure1-2.Figure1-2Meta-stableissue1.1.3.2GlitchLogicinthesynchronizationpathresultinglitchesduetopropagationdelays,theseglitchesmaygetlatchedandresultinfalsepulsesatthesynchronizeroutput,shownasfigure1-3.*Note:synchronizationpath:belowpathcanbedefinedassynchronizationpath,1.Pathfromsourceclockdomaintodestinationclockdomain,suchasthepathfromQofDA1/DA2totheDofDB1infigure1-3;2.PathfromQtoDoftwoflip-flopsindestinationclockdomain,suchasthepathfromQofDB1toDofDB2infigure1-3.Figure1-3Glitchissue1.1.3.3Multi-fanoutMulti-fanoutonthesynchronizationpathmayresultindifferentvalueatthesynchronizeroutputduetodifferentpropagationdelay,shownasfigure1-4.Figure1-4Multi-fanoutissue1.1.3.4Re-convergence（信号重汇聚）Re-convergencesignalsaftersynchronizationmayresultinfunctionalerror,asitisshownasfigure1-5.Figure1-5Re-convergenceissueRe-convergencelogicisaspecialCDCissuewhichneedlogicdesignerpaymoreattentionto,becauseallofCDCissueexceptRe-convergence,likemeta-stable,multi-fanoutandglitch,couldbedetectedbyCDCcheckingtool(forexamplecadence’sCONFORMAL).However,someofRe-convergenceissueissocomplexthatitishardtocheckbytools,takedeepre-convergenceissueforexample,whichisshownasfigure1-6.DFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFCLCLCLD0_AD0_BD0_CD0_DD3_E_synD3_F_synD3_G_synD1_AD1_BD1_CD1_DD2_AD2_BD2_CD2_DCLK_BCLK_BCLK_BCLK_BCLK_ACLK_ACLK_ACLK_AFigure1-6,Deepre-convergenceissueCLK_A_C:rhflrhflrhflrhflrhflrhflrhflrhflrCLK_B_C:llrflrflrflrflrflrflrflrflrflrflrfD0_A_reg:rhhhflllllllllllllllllllllllllllllD0_B_reg:rhhhflllllllllllllllllllllllllllllD0_C_reg:rhhhflllllllllllllllllllllllllllllD0_D_reg:rhhhflllllllllllllllllllllllllllllD1_A_reg:llllrhhhflllllllllllllllllllllllllD1_B_reg:llllrhhhflllllllllllllllllllllllllD1_C_reg:lllllrhhhfllllllllllllllllllllllllD1_D_reg:lllllrhhhfllllllllllllllllllllllllD2_A_syn:llllllllrhhfllllllllllllllllllllllD2_B_syn:llllllllrhhfllllllllllllllllllllllD2_C_syn:lllllllllllrhhflllllllllllllllllllD2_D_syn:lllllllllllrhhflllllllllllllllllllD3_E_syn:lllllllllllrhhflllllllllllllllllllD3_F_syn:llllllllllllllrhhfllllllllllllllllD3_G_syn:llllllllllllllllllllllllllllllllllFigure1-7Timingdiagramofdeepre-convergenceFromthefigure1-6,itcanfindthatthecircuithastwolevelsre-convergence,thefirstlevelre-convergencegateisflip-flopmarkedwithbluecolor,andthesecondisflip-flopmarkedwithredcolor.ForcadenceCDCtool,itwouldidentifyfirstlevelre-convergenceandreportthem,butitcannotidentifysecondlevelre-convergence.Whicheverlevelre-convergenceoccurred,itmayresultinfunctionalerror,asitisshownasfigure1-7.Itistoollimitation.1.1.4IMPLEMENTATIONThischapterintroducesseverallogicschemestodesignclockdomaincrossinglogiccorrectly.Theseschemescouldkeepdatatransferringstablybetweendifferentclockdomains.Nearlyalltheclockdomaincrossingissuecouldbeavoidedifdesignerfollowthedesignschemeintroducedinthechapter.1.1.4.1TwosynchronizerschemeForonebitsignalcrossdifferentclockdomain,ageneralsolutionisusingtwoflip-flopstosynctwocyclesindestinationclockdomain,butitspre-conditionisthesignalfromsourceclockdomainshouldholdlongenoughfordestinationclocktosample,inotherwords,thefrequencyofclockAshouldbelessthanclockB.Itscircuitcanbeshownasfigure1-8:FADQCKFB1DQCKFB2DQCKSignalAClockAClockBSignalBFigure1-8twoflip-flopsyncWhenusetwosynchronizerscheme,designershouldkeepnocombinationalcell(exceptinverterandbuffer)inCDCpath(*note),otherwise,glitchissueshowninfigure1-3andmulti-fanoutissueshowninfigure1-4mayoccurs.Note:CDCpath:thepathfromQofflip-flopinsourceclockdomaintotheDofflip-flopindestinationclockdomain,forexample,thepathfromFA/QtoFB1/Dinthefigure1-8.Asaexampleoftwosynchronizerapplication,figure1-9/1-10takeglitchandmulti-fanoutissueforexample,showshowtodesigntheselogic.CLKACLKBDA1DA2DB1DB2Figure1-9solutionofglitchissueCLKB