综合与Design-Compiler(很好)

DesignCompilerRTLDesignCompilerSynopsysHDLDesignCompiler§1.1.1141(translation)(mapping)(optimization)HDL(technology-independent)RTL(RTL)RTL1.222HDLHDLRTL1.2.1(instantiate)«VLSIhandbook»33331.2.2RTLRTLHDL33HDL(Inferencerule)always1.2.3RTLRTL(sequentialprogram)()5ns6ns3Tree()4546ns511ns2267RTL«VLSIhandbook»75611ns71.2.4DesignCompiler8DesignCompiler8DesignCompilerRTLRTLSynopsysBehaviorCompilerRTL1.3DesignCompiler9DCDCHDLRTLSynopsysDCgtech.dbRTL(constraints.tcl)(core_slow.db)1.41um0.5um(DSM:DeepSubMicrometer)0.25um(VDSM:VeryDeepSubMicrometer)gtech.db10VDSM0.5um70%(back-annotate)100.35um50%110.18um70%,(PhysicalSynthesisFlow)11VDSMPhysicalCompilerSynopsysDesignCompiler§2.VerilogVerilogVerilog(alwaysifcaseloop)VerilogHDLzzzRTL2.1alwaysalways(proceduralbehavior),always12alwaysDCVerilogHDLCompilerforVerilogReferenceManualUnsupportedVerilogLanguageConstructsalways(Verilog”@”)2.2Ifif13ififLatch14ifLatchMarks5GradeFAILMarks510GradePASSMarks10GradeGradeif…elseif…else15ifLatch2.3case2.3.1case(mutuallyexclusive)casecase162-bitALUcaseif…elseif…elseifcase(Op)casecase(ADD)(SUB)if2.3.2Casexcasexcasexz(don’t-care)casecasex17casexcasexifcasexcasexcase(casex0)2.3.3LatchcaseifcaseLatch18caseLatchZipToggle=03NextToggleLatchlatch(NextToggle)casedefaultcase2.3.4Full_case2.3.3caselatchcaseToggle2’b012’b10latch(synthesisdirective)synopsysfull_caseHDLHDLVerilogsynopsysfull_case19full_casefull_caseLatch1.2.Verilog2.3.5Parallel_case2.3.3casexif…elseif…elsecase(casecase)parallel_caseDesignCompilerVerilogHDLSynthesisAPracticalPrimer5case20parallel_casecasexifparallel_casefull_caseparallel_case2.3.6casecasecasecase21casefull_caselatch(Pbus1)latchcasecase2.4loopVerilogloopwhile-loop,for-loop,forever-looprepeat-loopfor-looploopFor-loop22looploopiflooploop2.5DesignCompileralways232-bitalwaysClockACounter1CounteralwaysalwaysalwaysCounter=Counter+1VerilogDesignCompiler()24DC21Q_regDesignCompilerAS2.6DCDesignWareDesignWareDC,==DesignWareDesignWareDesignWareBasicDesignWareFoundationDesignWareBasicDesignWareFoundation25DWFoundationDWBasicDWFoundationCarryLook-AheadRippleCarryFoundationDesignWareDesignWareFoundationLicesensynthetic_libraryverilogreginteger2627VerilogDesignCompiler§3.DesignCompilerSynopsysDesignCompilerz(Pre-synthesisProcesses)z(ContraintingtheDesign)z(SynthesizingtheDesign)z(Post-synthesisProcess)3.1DesignCompilerDCVerilogVerilog23.1.1DesignCompiler2000.11DesignCompilerDesignCompilerdc_shelldc_shell-tdesign_analyzerdesign_vision28DC1.dc_shellDesignCompilershell”dc_shell”dc_shelldcsh(dc_shell–fscript)2.dc_shell-tTCLToolCommandLanguageDesignCompilershell”dc_shell-t”dc_shell-ttcl(dc_shell-tfscript)TCLshellSynopsys3.design_analyzerDesignAnalyzerDesignCompilershelldesign_analyzerDesign_analyzerdc_shelldesign_analyzertclDesignanalyzerHDL4.design_visionDesign_visiontclshell”design_vision”WindowsNTdcshtclunixshelldcshtcldcshTCLTCLdcshDCTCLDesignAnalyzercommand.logview_command.logDesignCompilerfilenames.logdesigncompilerfilenames.logdesigncompilerdc_shellcommand.log3.1.2DesignCompiler1.(target_library)HDLsynopsysGTECHDesignCompilerFoundary.dbDC.db.lib.lib29(.lib)DCtarget_librarytcl2.(link_library)link_libraryDClink_libraryIPlink_library’*’,DCDCmemorylinklibrary’*’DCDCmemory(unresolveddesignreference)link_librarysearch_path30link_library(1)link_libraryDClinkTOPDECODElink_libraryDCDECODEsearch_pathlappendtclsearch_pathbob31link_library(2)3.(symbol_library)symbol_librarySchematicdesign_analyzerdesign_visionsymbol_library.sdbDCsetsymbol_library4.(synthetic_library)DCDesignWarestandard.sldbVerilogDesignWaresynthetic_librarylink_libraryDC3.1.3.synopsys_dc.setup32.synopsys_dc.setupDCDCDC1.$SYNOPSYS/admin/setupDC2.$HOME3.DCsetupdcshelltclDCUnixlsa”#”dcshellDCShell3.1.433DesignCompiler.db.v.vhddcshTCLreadformatverilog[dbvhdletc.]file//dcshread_dbfile.db//TCLDBread_verilogfile.v//TCLverilogread_vhdlfile.vhd//TCLVHDLDesignCompilerRTLDesignCompileranalyzeelaborateanalyzeHDLwork()elaborateverilogVHDLelaborateworklinkDesignCompilerlinkunresolveddesignreference.synopsys_dc.setuplink_libraryDCsearch_path3.1.534DCVerilogDCVerilog(Design)(Clock)(Port)(Net)(Reference)(Cell)(Pin)DCClockHDL35”CLK”5DCTCLcollectionCLK5getDCTCLTCL(list)CCCLK(fanout)get_netsTCLdcshelldc_shell-t”helpget*”getDC363.1.6(DesignPartition)(Divideandconquer)HDL(module)DCDC.37ACABCDCDCABCDC38DC39CDJKT.403738(GlueLogic)ABCCC41.()425003730TEENY43DesignCompiler/.44PadPadFoundryCoreDCDCASYNCHDCCLOCKGENPLLJTAGSynopsysBSDCompilerHDLDCHDLDCGroupUngroup””45groupgroupNEW_DES()U23U2U3ungroupU23U2U346ungroup3.2DesignCompiler(constrain-driven)DCTcl3.2.143RTLRTLRTLDCRTLRTLRTL3.2.1.1set_max_areaPRGRM_CNT_TOP100100Foundry1()report_area1,43.2.1.2DCNXS44FF2FF3XDCClkClkDCFF2FF310nsFF3(setuptime)1nsX10-1=9ns3.2.1.345(Clocksource)(DutyCycle)(ClockSkew)(ClockName)create_clock10nsClkdon’t_touchClkDCClkBuffer(ClockTree)DCFoundryns44XDC3.2.1.44647clk-qM20ns4ns1.0nsN20-4-1.0=15.0nsDCset_input_delayA4ns-maxsetuptime-min-clk3.2.1.548U3T20ns5.4nsU3clk-q1.0nsS20-5.4-1.0=13.6nsDCset_output_delayB5.4ns-max-clkzreport