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:900MHz2V13.62mWA2V13.62mW900MHzCMOSPhase-LockedLoopwithOn-ChipLoopFilter:A2V13.62mW900MHzCMOSPhase-LockedLoopwithOn-ChipLoopFilterStudent:Ying-ChunChiaAdvisor:Dr.Ro-MinWengAThesisSubmittedtoInstituteofElectricalEngineeringCollegeofSciencesandEngineeringNationalDong-HwaUniversityInPartialFulfillmentoftheRequirementsfortheDegreeofMasterinElectricalEngineeringJuly2003Hualien,Taiwan,RepublicofChina()900MHzTSMC0.35-µm1p4mCMOS;900MHz-102dBc/Hz600KHz6.2mWD2VHSPICElong-termjitter35ps13.62mW1.85µs:long-termjitter280ps14.1mW3.26µs(PAD)1688x1656µm2IABSTRACTCMOSphase-lockedloops(PLLs)areimportantcomponentswidelyusedintheelectronicandcommunicationcircuits.TheyareusedtosolvetheclockskewandfrequencysynthesisproblemsofICsinafastoperationspeedandhighlyintegratedenvironment.Inordertorealizesingle-chipRF-to-basebandsystems,highperformancePLLsarerequired.Therefore,themaingoalofcurrentdesignistoimplementon-chipPLLswithhigh-speed,low-phasenoise(low-jitter)andlow-powerconsumptionperformance.Inthisthesis,a900MHzPLLisdesignedwiththeTSMC0.35-µm1p4mlogicsilicideCMOSprocess.ThePLLconsistsatwo-stagevoltage-controlledringoscillator(ringVCO),afrequencydivider,aphasefrequencydetector(PFD)withchargepumpandanon-chippassiveloopfilter.TheringVCOhasadifferentialstructuretoreducethepower-supply-injectednoise.Onlytwodelaycellsareincludedintheoscillatortoachievehigh-frequencyoperationandminimizethepowerconsumption.At900MHzcarrierfrequency,thephasenoiseoftheVCOis–102dBc/Hzat600KHzfrequencyoffsetandthepowerconsumptionis6.2mW.Besides,inthefrequencydividerafastpipelinetechniqueusingsingle-phaseedge-triggeredratioedhigh-speedlogicflip-flopsandDflip-flopsisintroducedandanalyzed.Thetechniqueissuitableforrealizinghigh-speedsynchronouscounters.ThePFDdesignisfordead-zonefreetoreducethejitterofthePLL.Theloopfilterisasecond-orderlowpassfilter.Finally,with2Vsupplyvoltage,theHSPICEpre-simulationresultsIIshowthatthelong-termjitterofthePLLis35ps,thetotalpowerconsumptionis13.62mWandthelockingtimeis1.85µs.Thepost-simulationresultsshowthatthelong-termjitteris280ps,thepowerconsumptionis14.1mWandthelockingtimeis3.26µs.ThewholePLLchiparea(includingPAD)is1688x1656µm2.IIIIABSTRACTIIIVVIIXI11-111-1-111-1-231-2342-142-1-152-1-262-1-372-1-492-2102-2-1102-2-2112-3162-3-1162-3-218203-120IV3-1-1LC-tank203-1-2223-2233-2-1LC-tank243-2-2263-331384-1384-1-1384-1-2404-2484-2-1484-2-2(Dead-ZoneIssue)504-2-3PFD524-3554-3-1PLL554-3-2574-4(ProposedCPCircuit)584-561665-1665-1-1665-1-2685-1-3PLL69V5-1-4PLL725-2735-2-1735-2-2755-3785-48081VI1-121-2PLL21-3PLL22-142-252-3PFD(a)AB(b)AB72-4PFD82-582-6PFD102-7112-8122-9132-10132-11PLL152-12PLL162-13PLL162-14PLL172-15PLL193-1213-2LC-tank223-3223-4233-5LC-tankVCO(a)DCV(b)DC0V24DD3-6LC-tankVCO243-7PMOS25VII3-8PMOS263-9273-10283-11VCO303-12VCO303-13VCO313-14CMOS323-15333-16CMOS(N)ISF343-17ISFrmsΓ353-18VCO374-1(/16)394-2(Q)4014-3YuanSvenssonTSPCDFF404-443MOSCP2−4-5ClockingPseudo-NMOS434-644MOSCN2−4-7TSPCDFF454-8TSPCDFF454-9464-10474-11474-12484-13XOR494-14494-15PFD50VIII4-16PFD514-17524-18PFD524-19PFD534-20PFD544-21PFD544-22554-23564-24574-25574-26594-27Chang604-28604-29614-30614-31624-32624-33PLL645-1VCO()675-2VCO()675-350µA()685-450µA()685-5VCO()695-6()705-7()705-8()715-9()71IX5-10PLL725-11PLL725-12735-13(a)(b)745-14(a)(b)755-15765-16775-1777X3-1VCO364-1γPM654-2655-1()795-2()79XI1-11-1-1(CMOS)GHz:900MHz~GHz(GSMBluetoothWLAN…..)Mb/sGb/s(Skew)(1-1)(PhaseLockedLoopsPLLs)(1-2)[1]PLL(Reference)PLL1-31tT∆inCKBCKSkewClock−inDinDinCKBCKLCDigitalChipBuffer1-1inCKBCKPhase-LockedLoop1-2PLLPhaseDetectorRefLoopFilterVCOVout1-3PLLPLLPhaseDetector)(LoopFilter)(VCO)2PLL:(Acquisition)[2]PLL(ChargePump)PLL[3]()1-1-2900MHzCMOSPLLPLLPLL(SystemonChip)()(On-ChipLoopFilter)PLL[4]1-2;;;32-1PFDCPLPFVCOFrequencyDividerRefVout2-1[2]2-1:(Voltage-ControlledOscillatorVCO)(PhaseFrequencyDetectorPFD)(ChargePump)(LoopFilter)(FrequencyDivider)42-1-1(Voltage-ControlledOscillator)(LocalOscillation)2-2ctrlVoutfctrlVoutfoutfctrlV0f1f2f1V2VVCOK2-22-20f0=ctrlVVCOK(Hz/V)(TuningRange)12ff−:ctrlVCOoutVKff×+=0)12(−:∫∞−+×=tctrlVCOdttVKtfAtv])(22cos[)(0ππ)22(−5VV:ctrl])22cos[()(00φππ++×=tVKfAtvVCO)32(−0φctrlV)ctrl2(VCOVK××π;))(2(dttVKctrlVCO∫×πsKsVVCOctrloutπφ2)(=)42(−()2-1-2(FrequencyDivider):(GHz)(FrequencySynthesis);62-1-3(PhaseFrequencyDetectorPFD)(A)(B)()2-3AQBQ(a)(b)ABAQBQABAQBQtt2-3PFD(a)AB(b)AB2-3(a)ABABBQABφφ−QAQ02-3(b)ABAB0ABAB0AQBAAQBQQBQ2-3PFDPFD“”2-4:0A(PositiveAQBQ7Edge)PFD(=1=0)AQBQBPFD00B0=AQ1=BQ0=AQ0=BQ1=AQ0=BQStateStateState0BAAAB2-4PFDPFD2-5outVφ∆outVtφ∆2-5PFDoutVφ∆2-5:φ∆×=PDoutKV)52(−8PFD(V/rad)PFDPDKAQBQBAφφ−BAωω−(AB)(ChargePump)U(AcquisitionRange)(LockSpeed)AQBQPND2-1-4(ChargePump)(LoopFilter);PFD();PFD()PUAQ1SNDBQ2SVCO)PFD(Mismatch)I1=I2=I2-6PUND2-6:PIπφ2ePII×=)62(−eφPFD:BAeφφφ−=)72(−9:(DampingFactor)AQBQAQBQABABoutVoutVPCDDPFDIII==211I2IV2-6PFD2-22-2-1(Performance)102-1(Behavior)[5-6]2-7π2PIsKVCOπ21/M∑CPLPFVCODivider+-PFDeφ)(sFoutφinφfbφ2-72-7F(s)inφoutφ(rad/s)(A)(V)outφ(FrequencyDomain)M1(PhaseDomain)M1fbφinφPFDeφ2-72-2-211(2-8)2-7MsKCIsLVCOPP2)(×=)82(−MCKIsCKIsinP