What-is-the-Difference-Between-single--bc-wc--and-

2015/9/22WhatistheDifferenceBetweensingle,bc_wc,andon_chip_variationAnalysisModes?:013762Product:PrimeTimeLastModified:02/21/2008Question:Whatisthedifferencebetweenthesingle,bc_wc,andon_chip_variationanalysismodes?Answer:Thisarticlecoversthedifferencesbetweenthesingle,bc_wc,andon_chip_variationanalysismodesinPrimeTime.Itwillalsoexplainhowthesethreeanalysismodesareaffectedbythechosenslewpropagationmode(worst_sleworworst_arrival).Thefollowingtopicsarediscussed:TwoslewpropagationmodesTimingpathsandtheirproperanalysisThreetiminganalysismodesPotentialforoptimisminthesingleandbc_wcanalysismodesTwoSlewPropagationModesTimingpathsconsistofaseriesofcellsandnetsconnectedtogether.Thedelaysofthecellsandnetsrepresenttheamountoftimeittakesforasignaltransition(oredge)topropagateacrossthosecellsornets.ConsiderbuffercellsU1andU2connectedtogetherbynetn1,asshowninFigure1:Figure1:BufferToBufferExampleCircuitTherisingcelldelayacrosscellU1andtherisingnetdelayacrossnetn1canbeshowngraphicallybythewaveformsinFigure2:Figure2:HowCellAndNetDelayArcsAreMeasuredThedashedlinesinFigure2representthepointsatwhichthewaveformscrossthedelaythresholdvoltage(alsocalledthedelaytrippoint),whichistypically50%oftherailvoltage.Thecellandnetdelaysrepresenttheamountoftimebetweenthesevoltagethresholdcrossingpoints.Wecanalsoseetheslewdegradation,whichistheslowdownoftheslewrateduetoresistanceasittravelsalongthewire.Whendetailedparasiticsareannotatedonthedesignwithread_parasitics,PrimeTimeperformsdetailedRCdelaycalculationtocalculatetheslewsanddelays.Delaycalculationisperformedinstages,whereastageisdefinedasadrivingcellandthedrivennet.Theinputtransitionisappliedtothedrivingcell'sinput.Theresponseiscomputedatthedrivercell'soutputpinandthedownstreamloads,andthecell/netdelaysandpinslewsarederivedfromtheresponses:2015/9/22WhatistheDifferenceBetweensingle,bc_wc,andon_chip_variationAnalysisModes?:MeasuringStageResponseToDetermineDelaysAndSlewsStagedelaysandslewsareafunctionoftheinputtransitionrate,andthecharacteristicsoftheparasiticnetworkbeingdriven.Sincetheparasiticnetworksarefixed,theslewsaretherealdeterminingfactorindeterminingthedelay/slewcharacteristicsofthelogic.Slewsarepropagatedfromstagetostageinaforwarddirectiontodeterminethetimingofallstages.Sincetheoutputslewsofastageareinfluencedbytheinputslew,varyingtheslewatanypointwillaffecttheslews/delaysforseveraldownstreamstages.Figure4:PropagatingSlewsThroughTheDesignInthestringofbuffersabove,thepropagationofslewsisstraightforward.Wetaketheoutputslewfromeachgate'soutput,senditdownthewire,andfeeditintothenextgate'sinput.Whathappens,however,whentwoslewsarriveatthesamepoint?Thiscanhappenatacombinationalgate'soutputorataloadpinofamultidrivennet.PrimeTime(andforthatmatter,allstatictiminganalysistools)mustchooseoneoftheseslewstopropagateforward.Thesepointswhereaslewmustbechosenarecalledslewmergepoints,asshowninFigure5:Figure5:ExamplesOfSlewMergePointsLet'stakeacloserlookatthemostcommontypeofslewmergepoint,wheremultiplearcsarriveatagateoutput:Figure6:SlewMergePointAtCellOutputPinInthisexample,arcs(a)and(b)eachresultinauniqueslewarrivingatoutputpinU1/Z.Slew(a)atU1/Zarrivesfirstandhasaslowriserate.Slew(b)atU1/Zarriveslastandhasafastriserate.Thedecisionofwhichslewtopropagateisacrucialone,astheoutputslewdirectlycontrolsthecelldelaysandslewsofthedownstreamlogiccone.WhichslewdowepropagateforwardfromU1/ZintoU2/Aforamax-delaycalculation?TherearetwoslewpropagationmodesinPrimeTime:1.worst_slewpropagation-Inthismode,theworstslewischosenandpropagatedforward.Thisistheslowest(numericallylargest)slewformaxdelays,andthefastest(numericallysmallest)slewformindelays.Forourexamplecircuit,wewouldpropagatetheslowerslew(a)forwardintoU2/Aforamax-delaycalculation.ThisisthedefaultmodeforPrimeTimeandPrimeTimeSI.2.worst_arrivalpropagation-Inthismode,theslewwiththeworstarrivaltimeischosenand2015/9/22WhatistheDifferenceBetweensingle,bc_wc,andon_chip_variationAnalysisModes?(b)arriveslastatU1/Z,andwouldbepropagatedforwardintoU2/Aforamax-delaycalculation.Let'stakealookathowthisslewpropagationsettingwouldaffectthemax-delaypropagationofthetimingpathsthroughU1/AandU1/B:Figure7:SlewPropagationAndTimingPathsInworst_slewmode,theslowestslewisusedforedges(1)and(2).Thisisaccurateforthetimingpaththroughedge(1),andconservativeforthetimingpaththroughedge(2).Inworst_arrivalmode,thefasterandlater-arrivingslewisusedforedges(3)and(4).Thisisaccurateforthetimingpaththroughedge(4),butisoptimisticforthetimingpaththroughedge(3).worst_arrivalenablesustotrackslewsonaper-clockdomainbasis,sincearrivaltimesaremeasuredagainstareferencelaunchingevent(ourclockedge).Asaresult,thememoryandruntimerequir