超大规模集成电路第八次作业2016秋-段成华

Assignment81.Accessrelevantreferencebooksortechnicaldatabooksandgiveaccuratedefinitionsforthefollowingtimingparameters:(1)designentity,(2)signaldriver,(3)transaction,(4)event,(5)timequeue,(6)deltadelay,(7)simulationtime,(8)simulationcycle,(9)inertialtime,(10)transporttime.(1)designentity:InVHDLagivenlogiccircuitrepresentedasadesignentity.Adesignentity,inreturn,consistsoftwodifferenttypesofdescription:theinterfacedescriptionandoneormorearchitecturalbodies.Theinterfacedescriptiondeclarestheentityanddescribesitsinputsandoutputs.(2)signaldriver:IfaprocesscontainsoneormoresignalassignmentstatementthatschedulefuturevaluesforsomesignalX,theVHDLsimulatorcreatesasinglevalueholdercalledasignaldriver.(3)transaction:Apairconsistingofavalueandtime.Thevaluepartrepresentsafuturevalueofthedriver;thetimepartrepresentsthetimeatwhichthevaluepartbecomesthecurrentvalueofdriver.(4)event:It’sakindofsignalpropertyandpresentssignaljump.Suchasif(clk'eventandclk='1).(5)timequeue:It’susedtokeepsomesignaltransactionsinthesimulator.Timequeueentriesarerepresentedasatwo-tupleoftheform(SN,V),whereSNisasignalnameandVisthevaluethesignalisscheduledtoassumeatthescheduledtime.Eachtimequeueentryiscalledasignaltransaction.(6)deltadelay:Aperiodoftimegreaterthan0,butlessthananystandardtimeunitnonumberofdeltadelayaddedtogethercancausesimulationtimetoadvance.(7)simulationtime:Theelapsedtimeinstandardtimeunitsduringsimulation.(8)simulationcycle:Everytimesimulationtimeadvances,asimulationcycleoccurs,whichwenowdefinemoreformally.Theexecutionofamodelconsistsofaninitializationphasefollowedbytherepetitiveexecutionofprocessesintheprocessnetwork.Eachrepetitionissaidtobeasimulationcycle.(9)inertialtime:Example:Z=Iafter10ns;ThesignalpropagationwilltakeplaceifandonlyifinputIpersistsatagivenlevelfor10ns-theamountoftimespecifiedintheafterclause.(10)transporttime:Z=transportIafter10ns;AllchangesonIwillpropagatetoZ,regardlessofhowlongthevalueofIstaysatthenewlevel.2.ConstructVHDLmodelsfor74-139dual2-to-4-linedecodersusingthreedescriptiontypes,i.e.,behavioral,dataflowandstructuraldescriptions.SynthesizeandsimulatethesemodelsrespectivelyintheenvironmentofXilinxISEwiththeModelSimsimulatorintegrated.Whensimulatingthesemodels,testvector(s)arerequiredtostimulatetheunitsundertest(UUT).ReasonabletestvectorsaredesignedandcreatedbyyourownassourcesaddedtoyourVHDLproject.Logicschematicof74-139:Functiontableofonedecoderof74-139:INPUTSOUTPUTSENABLEGSELECTBAY0Y1Y2Y3HXXHHHHLLLLHHHLLHHLHHLHLHHLHLHHHHHL（1）、行为描述代码如下：--Company:--Engineer:--CreateDate:21:14:0912/02/2016--DesignName:--ModuleName:deceoder_beh-Behavioral--ProjectName:--TargetDevices:--Toolversions:--Description:--Dependencies:--Revision:--Revision0.01-FileCreated--AdditionalComments:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitydeceoder_behisPort(G1,G2:instd_logic;A:instd_logic_vector(1downto0);B:instd_logic_vector(1downto0);Y1:outstd_logic_vector(3downto0);Y2:outstd_logic_vector(3downto0));enddeceoder_beh;architectureBehavioralofdeceoder_behisbeginde1:process(A,G1)beginifG1='1'theny1=1111;--sequentialstatementelsecaseAiswhen00=Y1=1110;when01=Y1=1101;when10=Y1=1011;when11=Y1=0111;whenothers=Y1=1111;endcase;endif;endprocess;de2:process(B,G2)beginifG2='1'thenY2=1111;--sequentialstatementelsecaseBiswhen00=Y2=1110;when01=Y2=1101;when10=Y2=1011;when11=Y2=0111;whenothers=Y2=1111;endcase;endif;endprocess;endBehavioral;TestBench代码如下：--Company:--Engineer:--CreateDate:22:25:5912/02/2016--DesignName:--ModuleName:D:/ISE11.1_example/decoder/deconder_beh_tb.vhd--ProjectName:decoder--TargetDevice:--Toolversions:--Description:--VHDLTestBenchCreatedbyISEformodule:deceoder_beh--Dependencies:--Revision:--Revision0.01-FileCreated--AdditionalComments:--Notes:--Thistestbenchhasbeenautomaticallygeneratedusingtypesstd_logicand--std_logic_vectorfortheportsoftheunitundertest.Xilinxrecommends--thatthesetypesalwaysbeusedforthetop-levelI/Oofadesigninorder--toguaranteethatthetestbenchwillbindcorrectlytothepost-implementation--simulationmodel.LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.all;USEieee.numeric_std.ALL;ENTITYdeconder_beh_tbISENDdeconder_beh_tb;ARCHITECTUREbehaviorOFdeconder_beh_tbIS--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTdeceoder_behPORT(G1:INstd_logic;G2:INstd_logic;A:INstd_logic_vector(1downto0);B:INstd_logic_vector(1downto0);Y1:OUTstd_logic_vector(3downto0);Y2:OUTstd_logic_vector(3downto0));ENDCOMPONENT;--InputssignalG1:std_logic:='0';signalG2:std_logic:='0';signalA:std_logic_vector(1downto0):=(others='0');signalB:std_logic_vector(1downto0):=(others='0');--OutputssignalY1:std_logic_vector(3downto0);signalY2:std_logic_vector(3downto0);BEGIN--InstantiatetheUnitUnderTest(UUT)uut:deceoder_behPORTMAP(G1=G1,G2=G2,A=A,B=B,Y1=Y1,Y2=Y2);--Stimulusprocessstim_proc:processbegin--insertstimulu