PLL-noise仿真

SpectreRFWorkshopNoise-AwarePLLDesignFlowMMSIM7.1.1May2009Noise-AwarePLLDesignFlowMay2009ProductVersion7.1.12Contents1IntroductiontoNoise-AwarePLLDesignFlow..............................................................32DownloadingGPDK180..................................................................................................53BeforeStarting.................................................................................................................74Integer-NPLLdesignflow..............................................................................................94.1CreatingaCMIModelfortheVCO/Divider................................................................94.2CreatingaModelforthePFD/CP...............................................................................204.3SimulatinganInteger-NPLL......................................................................................285Fractional-NPLLDesignFlow.....................................................................................475.1CreatingaCMIModelfortheVCO/Divider..............................................................475.2CreatingaModelforthePFD/CP...............................................................................545.3SimulatingaFractional-NPLL...................................................................................54NoiseAwarePLLflowFAQ............................................................................................63Noise-AwarePLLDesignFlowMay2009ProductVersion7.1.131IntroductiontoNoise-AwarePLLDesignFlowPhase-lockedloops(PLLs)areusedtoimplementavarietyoftiming-relatedfunctions,suchasfrequencysynthesis,clockanddatarecovery,andclockde-skewing.AnyjitterorphasenoiseintheoutputofthePLLdegradestheperformancemarginsofthesysteminwhichtheyareusedandsoareofgreatconcerntodesigners.JitterandphasenoisearedifferentwaysofreferringtoanundesiredvariationinthetimingofeventsattheoutputofthePLL.TheyaredifficulttopredictwithtraditionalcircuitsimulatorsbecausethePLLgeneratesrepetitiveswitchingeventsasanessentialpartofitsoperation,andthenoiseperformancemustbeevaluatedinthepresenceofthislarge-signalbehavior.TheSpectreRFMMSIM6.2releaseintroducesatoolforpredictingthephasenoiseofaPLL-basedfrequencysynthesizerusingasimulationmethodthatisbothaccurateandefficient.ThemethodologyfirstpartitionsthePLLdesignintoafewbasicbuildingblocks,thenusestransistor-levelRFnoisesimulationtocharacterizethephasenoisebehavioroftheblocksthatmakeupthePLL.Foreachblock,thephasenoiseisextractedandappliedtoaphase-domainmodelfortheentirePLL.Thenextfigureillustratestheidea.Asanexample,thefollowingPLLdesignispartitionedintoafewbuildingblocks:VCO+Divider,PFD+CP,andtheLPF,whichisusuallyanout-of-chipcomponent.RVPFCPVCON÷FVClosedLoopPLLNoise100nV/√Hz200nV/√Hz500nV/√Hz1μV/√Hz2μV/√Hz5μV/√Hz10μV/√Hz20μV/√Hz50μV/√Hz1kHz10kHz100kHz1MHz10MHz100MHzAutomaticallygeneratemodelComputeJitterPSS-PNoiseADEtestbenchandAnalysisNoise-AwarePLLDesignFlowMay2009ProductVersion7.1.14SpectreRFprovidesacollectionoftestbenchesforthepartitionedbuildingblocks.ThespecializedVCO/Prescalertestbenchsupportssingle-endedVCOoutputs,phasesensitivitytotuningvoltage,andpositiveornegativepowersupplyconnects.ThesimpledividebyNisbuilt-inforafastersimulationbutdoesnotcarrynoiseproperties.ThePFDandCParecombinedtogetherinthesametestbench.Onlyatri-statePFDcircuittopologyissupported.Fundamentally,themodelsaresingle-endedandproducevoltages.Therearetwotypesofmodelscreated:CModelInterface(CMI)models,whicharenoteditableorviewable,andVerilog-Amodules,whichareviewableandeditable.TheVCO/PrescalermodelinthisworkshopiscreatedasaCMImodelandthePFD/CPmodeliscreatedasaVerilog-Amodule.Noise-AwarePLLDesignFlowMay2009ProductVersion7.1.152DownloadingGPDK180Topreparefortheworkshop,youfirstneedtocompletethedatabasebydownloadingtheCadence0.18umCMOSGenericProcessDesignKit(GPDK180).TogetacopyofGPDK180,Action2-1:Gotopdk.cadence.com.Action2-2:Registerasanewuser,thenlogin.Action2-3:ClickDownloads.Action2-4:SpecifyGenericforFoundry,0.18forSize,andMS/RFforMode.Action2-5:ClickSEARCHtosearchforapdkmatchingtheaboveattributes.Noise-AwarePLLDesignFlowMay2009ProductVersion7.1.16Action2-6:Downloadgpdk180_v3.3.tar.gzto./PLL_workshop.Action2-7:Moveintothe./PLL_workshopdirectory.Action2-8:Unpacktheworkshop.tar–zxfgpdk180_v3.3.tar.gzAction2-9:Createasymboliclinktogpdk180fromwhateverversionofthedesignkityoudownloaded.Forexample,ln–sgpdk180_v3.3gpdk180Noise-AwarePLLDesignFlowMay2009ProductVersion7.1.173BeforeStartingNote:Tousethenoise-awarePLLflowshowninthisworkshop,youmusthaveMMSIM7.1ISR5orlaterandoneofthefollowingICversions:•IC5.10.41.500.6.131•IC6.1.1.500.68•IC6.1.3.500.6•IC6.1.4•orlaterAction3-1:Moveintothe./PLL_workshopdirectory.Action3-2:Viewthecds.libfile.ThisfiledefinesthepathforthepllMMLiblibrary,whichislocatedat:CDS_HOME/tools/dfII/samples/artist/pllMMLibAction3-3:Viewthe.cdsinitfile.Noticethefollowinglineaddedforthisworkshop:envSetVal(spectre.envOptscontrolMode'stringbatch)ThisscriptmakestheSpectresimulatorruninbatc