Verilog-A-tutorial

TheWorldLeaderinHighPerformanceSignalProcessingSolutionsaTutorial:Howto(andHowNOTto)WriteaCompactModelinVerilog-AGeoffreyCoramAnalogDevices,Inc.2004IEEEBehavioralModelingandSimulationConference(BMAS2004)G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A2aIntroduction‹High-levellanguageforcompactmodelingislongoverdue‹Verilog-AisbecomingthestandardzAnalog-onlysubsetofVerilog-AMSzCompactmodelingextensionsinLRM2.2‹Remainingsteps:zCompactmodeldevelopersneedtobecomecomfortablezCompilersmustgeneratefastandreliablecodeG.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A3aWhatisaCompactModel?‹Amodeloftransistorcurrents&voltages‹Builtfromphysically-motivatedequations‹IntendedforuseinananalogcircuitsimulatorTCADmodelGate-levelmodelaccuracyspeedcompactmodelG.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A4aWhyVerilog-A?‹FasterimplementationcomparedtoC(orFORTRAN)zBSIM3self-heating:1-2daysinVerilog-Aversus2-3weeksinCzDerivativescodedautomaticallyG.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A5aWhyVerilog-A?‹FasterimplementationcomparedtoC(orFORTRAN)zBSIM3self-heating:1-2daysinVerilog-Aversus2-3weeksinCzDerivativescodedautomatically‹MultiplesimulatorsupportzAnalogDevices:Adice,Motorola/Freescale:MicazCadence:Spectre,MentorGraphics:Eldo,Synopsys:NanoSim,Agilent:ADS&ICCap,Silvaco:SmartSpice&UTMOST,…zNo*simulator-specificdetailsG.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A6aManymodels,manysimulatorsSpectreEldoADSSmashNanosimHSIMAPLACAMSGoldenGateHSPICEVBICHiCUMBSIMMextramACMHiSIMUSIMSPEKVMM11Source:C.McAndrew,etal,“ExtensionstoVerilog-AtoSupportCompactDeviceModeling”G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A7aManymodels,manysimulatorsSpectreEldoADSSmashNanosimHSIMAPLACAMSGoldenGateHSPICEVBICHiCUMBSIMMextramACMHiSIMUSIMSPEKVMM11Source:C.McAndrew,etal,“ExtensionstoVerilog-AtoSupportCompactDeviceModeling”G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A8aVerilog-AInterfaceTheSolutionSpectreEldoADSSmashNanosimHSIMAPLACAMSGoldenGateHSPICEVBICHiCUMBSIMMextramACMHiSIMUSIMSPEKVMM11Source:C.McAndrew,etal,“ExtensionstoVerilog-AtoSupportCompactDeviceModeling”G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A9aWhynotVerilog-A?‹ImplementationproblemszSlowperformancezPoorconvergencezInconsistentresultsbetweensimulators‹Missinglanguageconstructs‹Tooeasytocreate(bad)modelszDiscontinuitieszNon-physicalequationsthat“blowup”outsideexpectedrangez(butatleastthederivativesarealwaysright)G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A10aWhynotVerilog-A?‹ImplementationproblemszSlowperformanceCompiledinterfaceszPoorconvergencezInconsistentresultsbetweensimulators‹Missinglanguageconstructs‹Tooeasytocreate(bad)modelszDiscontinuitieszNon-physicalequationsthat“blowup”outsideexpectedrangez(butatleastthederivativesarealwaysright)G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A11aWhynotVerilog-A?‹ImplementationproblemszSlowperformancezPoorconvergenceMatureimplementationszInconsistentresultsbetweensimulators‹Missinglanguageconstructs‹Tooeasytocreate(bad)modelszDiscontinuitieszNon-physicalequationsthat“blowup”outsideexpectedrangez(butatleastthederivativesarealwaysright)G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A12aWhynotVerilog-A?‹ImplementationproblemszSlowperformancezPoorconvergencezInconsistentresultsbetweensimulators‹MissinglanguageconstructsCMextensions‹Tooeasytocreate(bad)modelszDiscontinuitieszNon-physicalequationsthat“blowup”outsideexpectedrangez(butatleastthederivativesarealwaysright)G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A13aWhynotVerilog-A?‹ImplementationproblemszSlowperformancezPoorconvergencezInconsistentresultsbetweensimulators‹Missinglanguageconstructs‹Tooeasytocreate(bad)modelszDiscontinuitiesVerilog-Adebuggers?zNon-physicalequationsthat“blowup”outsideexpectedrangez(butatleastthederivativesarealwaysright)G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A14aHowTO‹Verilog-Aisasimplelanguage‹Mostconceptscanbelearnedfromstudyingasimpleexample‹CanwriteBSIM3inVerilog-AusingonlytheconceptsdiscussedhereG.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A15aDiodeexample,p1`includedisciplines.vams`includeconstants.vamsmodulediode(a,c);inouta,c;electricala,c,int;branch(a,int)res;branch(int,c)dio;parameterrealis=10pfrom(0:inf);parameterrealrs=0.0from[0:inf);parameterrealcjo=0.0from[0:inf);parameterrealvj=1.0from(0:inf);G.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A16aDiodeexample,p1`includedisciplines.vams`includeconstants.vamsmodulediode(a,c);inouta,c;electricala,c,int;branch(a,int)res;branch(int,c)dio;parameterrealis=10pfrom(0:inf);parameterrealrs=0.0from[0:inf);parameterrealcjo=0.0from[0:inf);parameterrealvj=1.0from(0:inf);modulesreplaceSpiceprimitivesG.J.Coram:BMAS2004Tutorial:CompactModelinginVerilog-A17aDiodeexample,p1`includedisciplines.vams`includeconstants.vamsmodulediode(a,c);inouta,c;electricala,c,int;branch(a,int)res;branch(int,c)dio;parameterrealis=10pfrom(0:inf);parameterrealrs=0.0from[0:inf);parameterrealcjo=0.0from[0:inf);parameterrealvj=1.0from(0:inf);te