PLL-抖动

TheDesigner’sGuideCommunitydownloadedfrom©2005,KennethS.Kundert–AllRightsReserved1of31Version4f,November2005AmethodologyispresentedformodelingthejitterinaPhase-LockedLoop(PLL)thatisbothaccurateandefficient.ThemethodologybeginsbycharacterizingthenoisebehavioroftheblocksthatmakeupthePLLusingtransistor-levelsimulation.Foreachblock,thejitterisextractedandprovidedasaparametertobehavioralmodelsforinclu-sioninahigh-levelsimulationoftheentirePLL.ThisapproachisefficientenoughtobeappliedtoPLLsactingasfrequencysynthesizerswithlargedivideratios.LastupdatedonNovember6,[e-mail],eitherpaperorelectronic,ofthisworkforpersonalorclassroomuseisgrantedwithoutfeeprovidedthatthecopiesarenotmadeordistributedforprofitorcommercialadvantageandthatthecopiesarecompleteandunmodified.Todistributeother-wise,topublish,topostonservers,ortodistributetolists,requirespriorwrittenpermission.ModelingJitterinPLL-basedFrequencySynthesizersKenKundertModelingJitterinPLL-basedFrequencySynthesizersIntroduction2of31TheDesigner’sGuideCommunity(PLLs)areusedinwirelessreceiverstoimplementavarietyoffunctions,suchasfrequencysynthesis,clockrecovery,anddemodulation.OneofthemajorconcernsinthedesignofPLLsisnoiseorjitterperformance.JitterfromthePLLdirectlyactstodegradethenoisefloorandselectivityofatransceiver.DemirproposedanapproachformodelingPLLswherebyaPLLisdescribedusinghighlevelbehavioralmodels[1,2].Themodelsarewrittensuchthattheyincludejitterinanefficientway.Healsodevisedapowerfulnewsimulationalgorithmthatiscapableofcharacterizingthecircuit-levelnoisebehaviorofblocksthatmakeupaPLLthatisbasedonsolvingasetofnonlinearstochasticdifferentialequations[3,5].Finally,hegaveformulasthatcanbeusedtoconverttheresultsofthenoisesimulationsontheindi-vidualblocksintovaluesforthejitterparametersforthecorrespondingbehavioralmod-els[6].ThisapproachprovidesaccurateandefficientpredictionofPLLjitterbehavioroncethenoisebehavioroftheblockshasbeencharacterized.However,itrequirestheuseofanexperimentalsimulatorthatisnotreadilyavailable.ThispaperpresentstherelevantideasofDemir,butwhilehefocussedonpresentingtheconceptualaspectsofmodelingandsimulatingjitterinPLLs,thispaperconcentratesmoreonthepracticalaspects.ItpresentsalltheinformationadesignerwouldneedtopredictthenoiseandjitterofaPLLsynthesizer.Thispaperisanenhancedversionoftwopreviouspapers[13,14].Thejitterextractionmethodologyisbasedonthecommer-ciallyavailableSpectre®RF1simulator[24,25]andpresentsbehavioralmodelsforVer-ilog-A2,astandard,non-proprietaryanalogbehavioralmodelinglanguage[7,19].BothSpectreRFandVerilog-AareoptionstotheSpectrecircuitsimulator[12],availablefromCadenceDesignSystems.31.1PredictingNoiseinPLLsTherearetwodifferentapproachestomodelingnoiseinPLLs.Oneapproachistofor-mulatethemodelsintermsofthephaseofthesignals,producingwhatarereferredtoasphase-domainmodels.Inthesimplestcase,thesemodelsarelinearandanalyzedeasilyinthefrequencydomain,makingitsimpletousethemodeltopredictphasenoise,eveninthepresenceofflickernoiseorothernoisesourcesthataredifficulttomodelinthetimedomain.Phasedomainmodelsaredescribedmorefullyinthecompaniontothismanuscript[15].Theotherapproachformulatesthemodelsintermsofvoltage,andsoarereferredtoasvoltage-domainmodels.Theadvantageofvoltage-domainmodelsisthattheycanberefinedtoimplementation.Inotherwords,asthedesignprocesstransitionstobeing1.SpectreisaregisteredtrademarkofCadenceDesignSystems.2.VerilogisaregisteredtrademarkofCadenceDesignSystemslicensedtoAccellera.3.SpectreRFiscurrentlytheonlycommercialsimulatorthatiswellsuitedforcharacterizingthejitteroftheblocksthatmakeupaPLL.SPICEanditsdescendantsarenotsuitablebecausetheyonlyperformnoiseanalysisaboutaDCoperatingpointandsodonottakeintoaccountthetime-varyingnatureofthesecircuits.Harmonicbalancesimulatorsdoperformnoiseanalysisaboutaperiodicoperatingpoint,whichisacriticalprerequisite,buttheyhaveconvergence,accuracy,andperformanceproblemswithblockssuchasthePFD/CP,FDandVCOthatarestronglynonlinear.FrequencySynthesisModelingJitterinPLL-basedFrequencySynthesizers3of31TheDesigner’sGuideCommunity(SpectreRF),butitisalsocommonforthatnottobethecase.Forexample,afractional-Nsynthesizerdoesnothaveaperiodicoperatingpoint.Occasionally,thecircuitissensi-tiveenoughthatthenoiseaffectsthelarge-signalbehaviorofthePLL,suchaswithbang-bangclock-and-datarecoveryPLLs,whichinvalidatesanyuseofsmall-signalnoiseanalysis.Modelinglarge-signalnoiseinavoltage-domainmodelasavoltageoracurrentisprob-lem