MT6572_design_notice_V0.1--

loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseCopyright©MediaTekInc.Allrightsreserved.Copyright©MediaTekInc.Allrightsreserved.DesignnoticeV0.1(MT6572)loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUse1Contentintroduction--Blockdiagram--Baseband--Extendkey--GPIOSelection--SystemapplicationnoticeforUSBDownload--Nand+LPDDR1&LPDDR2--LCM--Camera--SDandeMMC--USB2.0HSloginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseCopyright©MediaTekInc.Allrightsreserved.Copyright©MediaTekInc.Allrightsreserved.Blockdiagramloginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUse3loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseCopyright©MediaTekInc.Allrightsreserved.Copyright©MediaTekInc.Allrightsreserved.Basebandloginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUsePinnamePinoutNormalmodeLP-DDR1NormalmodeLP-DDR2eFUSEEnablePMIC_SPI_CSNK220K-ohmPulltoGNDNopullFollowDDR1/2TESTMODEG4GNDGNDGNDFSOURCEAC24GNDGNDVGP2(2.0V)KCOL0C24Notpull-down,justfloatingorPU.RefertoUSBdownloadnotice•Fornormalusage,pleaseconfigureabovepinstobe“Normalmode”.－Allpinsmustfollow,otherwisesystemmaynotdownloadorboot-up•ForeFUSEEnable,pleasecontactMTKsupportwindowMT6572BBdesignnotice(DRAMtype,eFUSE)MUSTRead51.MT6572supportdifferenttypeDRAM.PleaseconfigurecorrectHWsettingforselectedDRAM.2.Ifyouwanttoenableefuse,followingHWconfigurationshouldbesetcorrectly.loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUsePinnamePinoutNormalmode(noJTAG)Debugmode(JTAGKP)Debugmode(JTAGMSDC1)Debugmode(JTAGCMRST)SIM1_SCLKH5Nopull20K-ohmPulltoVIO18Nopull20K-ohmPulltoVIO18SIM2_SCLKJ5NopullNopull20K-ohmPulltoVIO1820K-ohmPulltoVIO18MT6572BBdesignnotice(JTAG)2013-1-7JTMSJTCKJTMSJTCKJTDIJTDOJTMSJTCKJTDIJTDOSerialJTAGLegacyParallelJTAG/SerialJTAGR1=20KR2=NCR1=NCR2=20KR1=20KR2=20K6LegacyParallelJTAG/SerialJTAGMUSTReadJTAGinterfaceismuxedondifferentinterface.Youcanchooseoneofthemasyourwish,loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseMT6572BBdesignnotice(HWi2C)MT6572integrate2I2Ccontrollers,I2C_0andI2C_1I2C_0supportonlyoneI2Cinterface(1dedicate,Nomuxontootherpins)I2C_1supportuptofourI2Cmuxinterface(1dedicate,3muxtootherIO)PinnameControllerPinout1.8V2.8VIOtypeGPIOAuxmodeSCL_0I2C_0C25VVOpen-DrainAux.1(SCL)SDA_0C26Aux.1(SDA)SCL_1I2C_1B24VVAux.1(SCL)SDA_1B23Aux.1(SDA)CMRST2K25VXOpen-DrainorPush-Pull(SWconfigurable)Aux.2(SCL)CMPDN2L25VXAux.2(SDA)URXD2F26VXAux.3(SCL)UTXD2E26VXAux.3(SDA)BPI_BUS7A10VXAux.3(SCL)BPI_BUS8B10VXAux.3(SDA)MUSTReadexternalPull-upresistorrequirement[MUST]addpull-upresistorforopen-draini2C,recommend2.2K[Optional]baseonyoursystemdesign,reserveNCpull-upresistoratothermuxedi2C7loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseMT6572BBdesignnotice(Keymatrix)◎:pressthiskeywhenPower-ON(PWRKEY,Charging,RTCalarm)powersequenceisnormal△:pressthiskeywhenPower-ON(PWRKEY,Charging,RTCalarm)powersequenceisUSBDownloadnormalbootingwillproceedafter3secifUSBdownloadtool/cableisnotreadyPinnameKCOL0KCOL1KCOL2PinoutC24D24A25KROW0B25△◎◎KROW1A24◎◎◎KROW2B26◎◎◎GND△◎◎MUSTRead8loginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseMT6572BBdesignnotice(AnalogBBpower)MUSTRead9PinNamePinoutPowerBypassCap.FunctionDVDD18_MIPIRXT25VIO180.1uF,Note1MIPICSIDVSS18_MIPIRXU25GNDDVDD18_MIPITXR25VIO180.1uF,Note1MIPIDSIDVSS18_MIPITXP25GNDREFPF6(internal)1uF,Note1ABBreferencepowerREFNG6GNDAVDD18_USBH23VIO180.1uFUSBAVDD33_USBG24VUSB1uF(VUSBbypass)AVDD28_DACF1VTCXO0.1uFRFAPCAVDD18_MDD3VIO180.1uFRFIQDVDD18_PLLGPU9VIO180.1uFPLLAVDD18_APE5VIO180.1uF,Note2AUXADC,RTP•Note1:dedicateGNDBallmustconnecttocap,thenconnecttomainGND•Note2:ifAUXADCnotuse,capcansharewithAVDD18_MDPleasefollowthistableforMT6572analogBBpowerloginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseMT6572BBdesignnotice(EINT)MT6572’sMIPIportcanbeasEINT/MCINS,theseportdon’thaveinternalPU/PDNeedexternalpulluptoVIO18fortheseEINT/MCINS10MUSTReadExamplecircuit:addPUfortheEINT/MCINSloginid=[e-mail],time=2013-01-0717:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCXInternalUseMT6572B