集成电路设计-05-反相器动静态特性

EIS-WUHANUNIVERSITY1集成电路设计第五章CMOS反相器EIS-WUHANUNIVERSITY2Outline电路特性反相器CMOS反相器电压传输特性噪声容限传输延迟驱动大电容负载功耗及低功耗设计EIS-WUHANUNIVERSITY35-1特性成本复杂性和面积完整性和稳定性静态（稳态）特性性能动态（瞬态）特性能量效率能耗和功率EIS-WUHANUNIVERSITY45-2反相器（Inverter）VinVoutCLVDDCMOSInverterPolysiliconInOutVDDGNDPMOS2lMetal1NMOSContactsNWellEIS-WUHANUNIVERSITY5TwoInvertersConnectinMetalSharepowerandgroundVDDEIS-WUHANUNIVERSITY6CMOS反相器基本特点输出电源和GND噪声容限大逻辑电平与尺寸无关，可以采用最小尺寸稳态输出时，VDD或GND与输出之间总存在有限电阻的通路低输出阻抗对噪声和干扰不敏感极高的输入阻抗（inputresistance）稳态下Vdd和GND间无直流通路无静态功耗传输延迟（Propagationdelay）是负载电容和晶体管电阻的函数。EIS-WUHANUNIVERSITY7CMOSInverter——First-OrderDCAnalysisVOL=0VOH=VDDVM=f(Rn,Rp)VDDVDDVin=VDDVin=0VoutVoutRnRpEIS-WUHANUNIVERSITY8CMOSInverter:TransientResponsetpHL=f(Ron.CL)=0.69RonCLVoutVoutRnRpVDDVDDVin=VDDVin=0(a)Low-to-high(b)High-to-lowCLCLEIS-WUHANUNIVERSITY95-3VoltageTransferCharacteristicNMOS+PMOS图解法EIS-WUHANUNIVERSITY10I-VNMOS00.511.522.500.511.522.5VDS(V)X10-4VGS=1.0VVGS=1.5VVGS=2.0VVGS=2.5VNMOStransistor,0.25um,Ld=0.25um,W/L=1.5,VDD=2.5V,VT=0.4VEIS-WUHANUNIVERSITY11I-VPlot(PMOS)-1-0.8-0.6-0.4-0.200-1-2VDS(V)X10-4VGS=-1.0VVGS=-1.5VVGS=-2.0VVGS=-2.5VPMOStransistor,0.25um,Ld=0.25um,W/L=1.5,VDD=2.5V,VT=-0.4VAllpolaritiesofallvoltagesandcurrentsarereversedEIS-WUHANUNIVERSITY12PMOSLoadLinesVoutIDnVin=VDD+VGSpIDn=-IDpVout=VDD+VDSpVinVoutCLVDDEIS-WUHANUNIVERSITY13PMOSLoadLinesVDSpIDpVGSp=-2.5VGSp=-1VDSpIDnVin=0Vin=1.5VoutIDnVin=0Vin=1.5Vin=VDD+VGSpIDn=-IDpVout=VDD+VDSpEIS-WUHANUNIVERSITY14CMOSInverterLoadCharacteristicsIDnVoutVin=2.5Vin=2Vin=1.5Vin=0Vin=0.5Vin=1NMOSVin=0Vin=0.5Vin=1Vin=1.5Vin=2Vin=2.5Vin=1Vin=1.5PMOSEIS-WUHANUNIVERSITY15CMOSInverterVTCVoutVin0.511.522.50.511.522.5NMOSresPMOSoffNMOSsatPMOSsatNMOSoffPMOSresNMOSsatPMOSresNMOSresPMOSsatEIS-WUHANUNIVERSITY16噪声容限logic1logic0unknownVDDVSSVHVL反映了对噪声的敏感程度；电路0，1电平允许的输入范围；越大越好；高电平噪声容限低电平噪声容限EIS-WUHANUNIVERSITY17LogiclevelmatchingLevelsatoutputofonegatemustbesufficienttodrivenextgate.EIS-WUHANUNIVERSITY18TransfercharacteristicsTransfercurveshowsstaticinput/outputrelationship—holdinputvoltage,measureoutputvoltage.EIS-WUHANUNIVERSITY19反相器噪声容限的三种求法求法1最低输出高电平、最高输出低电平；找到对应的输入；求差；VNL=Voff–VilVNH=Vih–VonVolVol,maxVoh,minVohVonVihVoffVilEIS-WUHANUNIVERSITY20求法2单位增益点（斜率为1，-1）；找到对应的输入；求差；VNL=Voff–VilVNH=Vih–VonVolVol,maxVoh,minVohVonVihVoffVilEIS-WUHANUNIVERSITY21求法3工作中心点；Vin=VoutVgs=Vds找到对应的输入；求差；EIS-WUHANUNIVERSITY22NoiseMarginsDeterminingVIHandVIL0123VILVIHVinVOH=VDDVMBydefinition,VIHandVILarewheredVout/dVin=-1(=gain)VOL=GNDApiece-wiselinearapproximationofVTCNMH=VDD-VIHNML=VIL-GNDApproximating:VIH=VM-VM/gVIL=VM+(VDD-VM)/gSohighgaininthetransitionregionisverydesirableEIS-WUHANUNIVERSITY23CMOSInverterVTCfromSimulation00.511.522.500.511.522.5Vin(V)Vout(V)0.25um,(W/L)p/(W/L)n=3.4(W/L)n=1.5(minsize)VDD=2.5VVM1.25V,g=-27.5VIL=1.2V,VIH=1.3VNML=NMH=1.2(actualvaluesareVIL=1.03V,VIH=1.45VNML=1.03V&NMH=1.05V)Outputresistancelow-output=2.4khigh-output=3.3kEIS-WUHANUNIVERSITY24VM与PMOS及NMOS的宽长比0.80.911.11.21.31.41.50110(W/L)p/(W/L)nIncreasingthewidthofthePMOSmovesVMtowardsVDDIncreasingthewidthoftheNMOSmovesVMtowardGND决定因素：宽长比近似为等效电阻之比。.1工艺因子：k’=µCox导电因子：βn=k’（W/L）~3.4Rn≈1/[βn(Vgs–Vt)]EIS-WUHANUNIVERSITY25GainDeterminates-18-16-14-12-10-8-6-4-2000.511.52VinGainisastrongfunctionoftheslopesofthecurrentsinthesaturationregion,forVin=VM(1+r)g----------------------------------(VM-VTn-VDSATn/2)(ln-lp)Determinedbytechnologyparameters,especiallychannellengthmodulation(l).OnlydesignerinfluencethroughsupplyvoltageandVM(transistorsizing).EIS-WUHANUNIVERSITY26GainasafunctionofVDD00.050.10.150.200.050.10.150.2Vin(V)Vout(V)00.511.522.500.511.522.5Vin(V)Vout(V)Gain=-1100mv时，VTC变差；过渡区增益接近-1一般，为达到足够的增益，电源应大于热电势的两倍VDDmin2,4KT/qKT/q室温下约为26mvEIS-WUHANUNIVERSITY27SimulatedVTC00.511.522.500.511.522.5Vin(V)Vout(V)EIS-WUHANUNIVERSITY28ImpactofProcessVariations00.511.522.500.511.522.5Vin(V)Vout(V)GoodPMOSBadNMOSGoodNMOSBadPMOSNominalEIS-WUHANUNIVERSITY295-4传输延迟（PropagationDelay）EIS-WUHANUNIVERSITY30DelayAssumeidealinput(step),RCload.EIS-WUHANUNIVERSITY31tpHL=f(Ron.CL)=0.69RonCLVoutVoutRnRpVDDVDD(a)Low-to-high(b)High-to-lowCLCL上升时间（risetime）,pullupon;下降时间（falltime）,pullupoff.EIS-WUHANUNIVERSITY32CurrentthroughtransistorTransistorstartsinsaturationregion,thenmovestolinearregion.Vout增大充电电流减小。Vds减小。EIS-WUHANUNIVERSITY33Resistiveapproximation可使用积分求解等效电阻平均值VGSVTRonSDEIS-WUHANUNIVERSITY34Req——求VDD/2，VDD区间的电阻平均值EIS-WUHANUNIVERSITY35GatedelayDelay:传输延迟VDD50%VDD50%VDDVDDTransitiontime:转换时间timerequiredforgate’soutputtoreach10%(logic0)or90%(logic1)offinalvalue.10%90%90%10%EIS-WUHANUNIVERSITY36InverterdelaycircuitLoadisresistor+capacitor,driverisresistor.EIS-WUHANUNIVERSITY37Inverterdelaywithtmodeltmodel:gatedelaybasedonRCtimeconstantt.Vout(t)=VDDexp{-t/(Rn+RL)CL}90%(logic1)10%(logic0)tf=2.2RCL100%(logic1)50%tD=0.69RCLForpulluptime,usepullupresistance.EIS-WUHANUNIVERSITY38tmodelinverterdelay0.5micronprocess:Rn=3.9kCL=0.68fF延迟时间td=0.69x3.9x0.68E-15=1.8ps.上升延迟tf=2.2x3.9x0.68E-15=5.8p