ICC-work-shop-Design-Planning

12-Agenda©2010Synopsys,Inc.AllRightsReservedSynopsys20-I-071-SSG-010DAY1Introduction&OverviewiDataSetup&BasicFlow1DesignPlanning222-UnitObjectivesAftercompletingthisunit,youshouldbeableto:UseICCompilertocreateanon-hierarchicalchip-levelfloorplanCreateafloorplanthatislikelytoberoutableandachievetimingclosure32-GeneralICCompilerFlowSynthesisDataSetupDesignPlanningPlacementClockTreeSynthesisRoutingChipFinishingThisUnit42-TerminologyDesignplanningistheiterativeprocessofcreatingafloorplanAchip-levelfloorplanentailsdefining:Coresize,shapeandplacementrowsPeriphery:IO,power,cornerandfillerpadcelllocationsMacrocellplacementStandardcellplacementconstraints(blockages)Powergrid(rings,straps,rails)Aphysicaldesign,orlayout,istheresultofasynthesizednetlistthathasbeenplacedandrouted52-Re-synthesisICCDesignPlanningandRe-SynthesisFlowDesignPlanning(ICC)VirtualflatplacementCreatestartingfloorplanReducedelaySynthesizepowernetworkReducecongestionWriteoutDEFfileRTLre-synthesiswithDEFfloorplan(DC-Topo)Datasetupwithre-synthesizednetlist(ICC)ReadDEFfile(ICC)PlacementRTLsynthesiswithdefaultfloorplan(DC-Topo)Datasetup(ICC)Designplanningwitha2-passsynthesisflowImprovedQoR62-CreateStartingFloorplanCreatetheStartingFloorplanInitializethefloorplanSpecifypadcelllocationsCreatephysical-onlypadcellsDefineknownpowerstructureDefineknownmacro/stdcellplacementSpecifyignoredroutinglayersDefineknownplacementblockagesDesignPlanningVirtualflatplacementCreatestartingfloorplanOptimize/analyzetimingSynthesizepowernetworkAnalyze/optimizecongestionWriteoutDEFfileDC-TsynthesiswithdefaultfloorplanDatasetupStartingFloorplanPlacementReduceCongestionPNSReduceDelayWriteDEFStartingFloorplanCreateP/GpadringsInsertpadfillercells72-SelecttheDesignPlanningTaskGUIopen_mw_celDESIGN_data_setupset_tlu_plus_files\-max_tluplus./libs/abc_max.tlup\-min_tluplus./libs/abc_min.tlup\-tech2itf_map./libs/abc.mapsourcetim_opt_ctrl.tclgui_set_current_task–name{DesignPlanning}Thismakesadditionalmenusandformsavailable,whichareotherwisehiddenRe-applyTLUplusRe-applytimingandoptimizationcontrols82-CreatePhysical-onlyPadCellsPhysical-onlypadcells(VDD/GND,cornercells)arenotpartofthesynthesizednetlistMustbecreatedpriortospecifyingthepadcelllocationscreate_cell{vss_lvss_rvss_tvss_b}pv0icreate_cell{vdd_lvdd_rvdd_tvdd_b}pvdicreate_cell{CornLLCornLRCornTRCornTL}pfrelrStartingFloorplan92-SpecifyPadCellLocationsA_1A_0vss_lpad_data_0pad_data_2vdd_lpad_data_1CornLLClk231…#Placethecornercellsset_pad_physical_constraints-pad_name“CornUL”-side1set_pad_physical_constraints-pad_name“CornUR”-side2set_pad_physical_constraints-pad_name“CornLR”-side3set_pad_physical_constraints-pad_name“CornLL”-side4#Placeioandpowerpads#Left/Rightsidesstartfrombottom(excludingcorner)set_pad_physical_constraints-pad_name“pad_data_0”\-side1–order1set_pad_physical_constraints-pad_name“pad_data_1”\-side1–order2set_pad_physical_constraints-pad_name“vdd_l”\-side1–order3....#Bottom/Topsidesstartfromleft(excludingcorner)set_pad_physical_constraints-pad_name“Clk”\-side4–order1set_pad_physical_constraints-pad_name“A_0”\-side4–order2....set_pad_physical_constraints\–pad_namename–side#–order#Constraintsarehonoredwhenthefloorplaniscreated,withevendistributionbydefaultStartingFloorplan231…231…231…Side1Side3Side2Side4UL=Side1UR=Side2LR=Side3LL=Side4102-InitializetheFloorplanCreatesthecoreandperipheryareaDefinesplacementorsiterowswithinthecoreareaDefinesthechipboundaryorperipheryareaPlacesIOpadsPadsdefinedinnetlistandbycreate_cellOrderingdefinedbyset_pad_physical_constraintsinitialize_floorplan...StartingFloorplan112-CoreAreaParametersControlType*AspectratioCoreutilizationAspectratio(H/W)Row/coreratio*WidthandheightCorewidthCoreheightRow/coreratio*……….*……….Exampleofahorizontal,nodoubleback,no-flipfirstrowandRow/core1.0Row1Row3Row2TopofrowkeyCoretobottomdistanceCoretorightdistanceCorewidthCoreheightStartingFloorplan122-FloorplanAfterInitializationUnplacedMacrocellsUnplacedStandardcellsCoreareawithsiterowsPeripherywithI/OpadcellsStartingFloorplan132-InsertPadFillerCellsStartingFloorplanA_1A_0VSS_LEFTpad_data_0pad_data_2VDD_LEFTpad_data_1CornerLLClkMaybeneededforcontinuityofN-well,P-well,and/orP/Groutinginsert_pad_filler–cellfill5000fill2000fill1000...fill2000fill500fill1000fill500fill500fill500PadfillercellsOrderofcellsisimportant–listlargesttosmallestfromlefttorighttouseminimumnumberofcells!142-CreateP/GPadRingsStartingFloorplanRouteP/GringsVDDQVDDOVDDVSSQVSSOVSSVDDQVDDOVDDVSSQVSSOVSSderive_pg_connection-power_netVDD-power_pinVDD-ground_netVSS-ground_pinVSSderive_pg_connection-power_netVDDO-power_pinVDDO-ground_netVSSO-ground_pinVSSOderive_pg_connection-power_netVDDQ-power_pinVDDQ-ground_netVSSQ-ground_pinVSSQderive_pg_connection-power_netPWR-ground_netGND–tiecreate_pad_ringsMaybeneededforP/GcontinuityMakelogicalP/Gpinconnections152-PriortoVirtualFlatPlacementBydefaultvirtualflatplacement(create_fp_placement):Placesstandardcellsandnon-fixedmacrosCanplacecellsanywhereinthecoreAssumesalllayersdefinedinth