ICC-work-shop-Finishing

16-Agenda©2010Synopsys,Inc.AllRightsReservedSynopsys20-I-071-SSG-010DAY3ClockTreeSynthesis(Labcontinued)4Routing5ChipFinishing6CustomerSupportCS26-UnitObjectivesAftercompletingthisunit,youshouldbeabletoperformkeychipfinishinganddesignformanufacturingstepsrequiredaftersignalroutingiscomplete:FixantennaviolationsModifytheroutingpatternstomakethemmoreresistanttodefectsAddredundantcontactsPerformmetalfillingInsertfillercells36-ICCompilerFlowSynthesisDataSetupDesignPlanningPlacementClockTreeSynthesisRoutingChipFinishing46-DesignStatus,CompletionofRoutingPhasePlacement–completedClockTreeSynthesis–completedPower/Signal/Clocknets–routedSetup/Holdtiming–Met(positiveslack)LogicalDRC–maxcap/transition–noviolationsPhysicalDRC–noviolations56-ChipFinishingFlowPost-Route:Timing&DRCcleandesignReducecriticalareaFixantennaviolationsInsertfillercellsPerformincr.timingopt.InsertredundantviasInsertmetalfill66-Centerofconductivedefectswithincriticalarea–causingshortsCenterofnon-conductivedefectswithincriticalarea–causingopensRandomParticleDefectsRandomparticledefectsduringmanufacturingmaycauseshortsoropensduringthefabricationprocessWiresatminimumspacingaremostsusceptibletoshortsMinimum-widthwiresaremostsusceptibletoopensCriticalAreaAntennaFillerCellsInc.TimingOpt.RedundantViasMetalFillCriticalAreaCriticalAreasMetal3Centerofconductivedefectsoutsidecriticalarea–noshortsCenterofnon-conductivedefectsoutsidecriticalarea–noopens76-ReportingtheCriticalAreaGeneratesbothtextualandgraphicaloutputreport_critical_area-particle_distr_func_filefile-input_layers{m2m3m4}-fault_type{short|open}86-DiscreteDefectSizeDistributionDefectsizedistributionfunctiondependsonthefabricationprocessICCompileracceptsdiscretedefectsizesandtheirprobabilitiesinatableformatAnexampleDefectSizeProbability0.200.0027780.360.0009220.520.0004120.680.0002190.840.000130…...96-Solution:WireSpreading+WireWideningWireTracksSpreadingoff-trackby½pitchWideningspread_zrt_wires\-timing_preserve_setup_slack_threshold.05\-timing_preserve_hold_slack_threshold.05widen_zrt_wires\-timing_preserve_setup_slack_threshold.05\-timing_preserve_hold_slack_threshold.05106-WireSpreading:spread_zrt_wiresWirespreadingPostroutefunctionforreducingcriticalareaforshortsSpreadsignalwiresby½pitchoruser-specifiedamountOnlyspreadinpreferreddirectionAutomaticsearchandrepairtofixDRCsTimingpreservation(optional)spread_zrt_wires-pitchreal;#ofpitchestospread,defaultis0.5-min_jog_lengthint;#Minimumjoglengthinlayerunitonpreferreddirection,defaultis2-timing_preserve_setup_slack_thresholdreal-timing_preserve_hold_slack_thresholdreal116-ControllingMinimumJogLengthPushingwiresoff-trackalwayscreatesajogandincreaseswirelengthUse-min_jog_lengthoptiontocontroltheminimumjoglength(default:2pitches)Willnotpushawireunlesstheavailablespaceislargerthan‘-min_jog_length’joglengthjoglength126-WireWidening:widen_zrt_wiresWirewideningPostroutefunctionforreducingcriticalareaforopensWillnottriggernewfatspacingruleswhenwideningAutomaticsearchandrepairtofixDRCsTimingpreservation(optional)widen_zrt_wires-timing_preserve_setup_slack_thresholdreal-timing_preserve_hold_slack_thresholdreal-timing_preserve_netstimingpreservenets136-Duringetchphase,thediodeclampsthevoltageswings.FixRemainingAntennaViolationsw/DiodesBeforeinsertingdiodesDiodeInhibitslargevoltageswingsonmetaltracksCriticalAreaAntennaFillerCellsInc.TimingOpt.RedundantViasMetalFillAntenna146-AntennaFixingwithDiodeInsertionDiodeinsertionisalsoconcurrentwhenenabledItisNOTrecommendedduringdetailedrouteUsediodestofixantennaviolationsthatarenotfixablebylayerjumping:Canspecifydiodenames(automaticifnonespecified)set_route_zrt_detail_options\-antennatrue\-insert_diodes_during_routingtrue\-diode_libcell_names{adiode1adiode2}route_zrt_detail-incrementaltrue156-WhyFillerCellInsertion?Forbetteryield,densityofthechipneedstobeuniformSomeplacementsitesremainemptyonsomerowsICCcanfillsuchemptysiteswithstandardfillercellsCriticalAreaAntennaFillerCellsInc.TimingOpt.RedundantViasMetalFillFillerCells166-InsertFillerCellsinUnusedPlacementSitesAddfillercellswithmetalfirstForDRCcheckingpurposes,standardcellPGrailsshouldbecompletepriortoinsertingfillercellswithmetalThenaddfillercellswithoutmetalinsert_stdcell_filler\–cell_with_metalfillCap64fillCap32\-connect_to_powerVDD–connect_to_groundVSS\-between_std_cells_onlyinsert_stdcell_filler\-cell_without_metalfill16...Fill1-connect_to_powerVDD–connect_to_groundVSS\-between_std_cells_only176-IsIncrementalTimingOptimizationNeeded?Criticalarea,antennafixingorfillercellinsertioncancreatesmalltimingviolationsCanperformincrementaltimingoptimizationbyre-sizingtheexistingcellsCriticalAreaAntennaFillerCellsInc.TimingOpt.RedundantViasMetalFillInc.TimingOpt.route_opt–incremental–size_only186-VoidsinViasduringManufacturingDuringroutingphase:Duringchipfinishingphase:CriticalAreaAntennaFillerCellsInc.TimingOpt.RedundantViasMetalFillRedundantViasset_route_zrt_common_options\-post_detail_route_redundant_via_insertionmediu