ICC-work-shop-cts

14-Agenda©2010Synopsys,Inc.AllRightsReservedSynopsys20-I-071-SSG-010DAY2Placement3ClockTreeSynthesis4DesignPlanning(Lab–continued)224-UnitObjectivesAftercompletingthisunit,youshouldbeableto:ListthestatusofthedesignpriortoCTSSetupthedesignforclocktreesynthesisIdentifyimplicitclocktreestart/endpointsandwhenexplicitmodificationsareneededControltheconstraintsandtargetsusedbyCTSExecutetherecommendedclocktreesynthesisandoptimizationflowAnalyzetimingandclockspecificationspostCTS34-GeneralICCompilerFlowSynthesisDesignSetupDesignPlanningPlacementClockTreeSynthesisRoutingChipFinishingThisUnit44-ICCompilerClockTreeSynthesisFlowThe“CTSphase”involvesseveralkeysteps:SetupstepstocontrolCTSOptionalPre-CTSpoweroptimizationClockTreeSynthesisTimingOptimizationRoutingofclocknetsNote:Theflowdiagramsincludedinthisunitrepresentanexampleflow,nottherecommendedflowClockTreeSynthesisClockTreeSynthesisTimingOptimizationClocknetroutingPre-CTSClockTreePowerOptimizationCTSSetupPlacementRouting54-DesignStatusPriortoClockTreeSynthesisPlacement-completedPowerandgroundnets–preroutedEstimatedcongestion–acceptableEstimatedsetuptiming–acceptable(~0nsslack)Estimatedmaxcap/transition–noviolationsHighfanoutnets:Reset,ScanEnablesynthesizedwithbuffersClocksarestillnotbuffered64-StartingPointbeforeCTSFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFClockAllclockpinsaredrivenbyasingleclocksource.74-ClockCellsAreInsertedandthenResizedBuffersareinsertedtobalancetheloads,meetDRCsandminimizetheskewFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFClock84-DelayCellsAreAddedtoMeetMin.InsertionDelaycellsareplacedbehindthecommonsinglebuffertominimizeclockskewimpactFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFClock94-CTSGoalsMeettheclocktreeDesignRuleConstraints(DRC):MaximumtransitiondelayMaximumloadcapacitanceMaximumfanoutMaximumbufferlevelsMeettheclocktreetargets:MaximumskewMinimuminsertiondelayConstraintsareupperboundgoals.Ifconstraintsarenotmet,violationswillbereported.Targetsarenicetohavegoals.Iftargetsarenotmet,noviolationswillbereported.104-ClockTreeSynthesisClockTreeSynthesisTimingOptimizationClocknetroutingPre-CTSClockTreePowerOptimizationCTSSetupPlacementRoutingICCompilerClockTreeSynthesisFlowNDRsTargetsConstraintsControl114-DefaultClockTreeTargetsThedefaultCTStargetforskewandinsertiondelayis0nsUncertaintyandinsertiondelaySDCconstraintsareignoredItisrecommendedtorelaxtheclockskewtargetasmuchaspossibleReducesoverallbuffercountandruntimeSpecifyminimumclocklatenciesasneededTargets124-SpecifyingGlobalTargetsicc_shellset_clock_tree_options\-target_early_delay0.9\-target_skew0.1SettingglobalCTSoptions...1OptionscanbesetonallclocksdefinedinSDC(globally)oronaclock-by-clockbasis.134-SpecifyingClock-SpecificTargetsUsetheGUI,selecttheappropriateclockfromthepull-down,andOKyourselectionsforeveryclockBetter:Howdoyousetdifferenttargetsperclock?set_clock_tree_options\–clock_treesclk1-target_early_delay0.9set_clock_tree_options\–clock_treesclk2-target_skew0.2TIP:UsetheGUIpreviewmode,thencut&pastetheecho’dcommandsintoyourscript.144-ControlBuffer/InverterSelectionTosetspecificbuffers/inverterstobeusedduringeachofthespecificCTSoptimizations:set_clock_tree_references–referenceslist1(DRCbuffering)–referenceslist2–sizing_only(skewbalancing)–referenceslist3–delay_insertion_onlyThereisnopriorityonhowCTSusesthemembersfromeachlistIfalistisnotspecified,bydefaultallbuffers/inverters(exceptdont_usecells)inthelibrarycanbeusedduringitsrespectiveoptimizationItisrecommendedtodefinealllistsMakesurethereferencesareintarget_library!154-CHIP_TOPAreallClockDriversandLoadsSpecified?MOD_Acbuf10MOD_Bcbuf2cbuf2cbuf6set_driving_cellset_input_transitionset_loadConstraints164-Remove“Skew”fromUncertaintyYourSDCconstraintswillmostlikelyincludeaset_clock_uncertainty–setupnumberappliedtoeachclockThiscommandisusedtomodelestimatedclockskew,butcanalsobeusedtomodeltheeffectsofclockjitterandtoincludesomeadditionaltimingmarginThespecifiedsetupnumberreducestheeffectiveclockperiodofallpathscapturedbythespecifiedclockandisusedduringsynthesistoestimateclockbehaviorTiminganalysispost-CTSwillalsoincludetheeffectsofthiscommand,therefore:RemoveclockuncertaintyifonlyskewisincludedORReducetheuncertaintynumberbytheestimatedskewremove_clock_uncertainty[all_clocks]174-DefiningCTS-SpecificDRCValuesMaxtransitionandmaxcapacitancedesignrulescanbespecifiedinthreeways:Library,SDCandCTSsettingBydefaultICCompilerwillusethesmallestofthethreeThedefaultCTSsettingsaresetfortoday’stechnologiesIfusing90nmyoumayneedtorelax(increase)thenumbers184-WhereDoestheClockTreeBeginandEnd?StartDQFFCLKGATEDCLOCKDQFFCLKDQFFCLKSTOPSTOPSTOPControlSynthesizableclocktreesend(bydefault)onclockpinsofregistersormacros(stoporfloatpins)EndClocktreesstartattheir“source”definedbycreate_clock…194-Stop,FloatandExcludePinsStopPins:CTSoptimizesforDRCandclo