smic13-ICC-flow-Allen

SMIC13ICCFlowIntroductiontoDevelopersAllen.Yang@XmartTheICdesignbackendtrainingitemlist•ICcompilertrainingoverview•ICCandP&Rflowoverview•PVtoolcalibreoverview•PVDRC/LVSflowoverview•STAPrimeTimeoverview•StarRCXTtooloverview•ICCompilerisanintegralpartoftheSynopsysGalaxy™ImplementationPlatformthatdeliversacomprehensivedesignsolution,includingsynthesis,physicalimplementation,low-powerdesign,anddesignformanufacturability.•ICCompilerisasingle,convergent,chip-levelphysicalimplementationtoolthatincludesflatandhierarchicaldesignplanning,placementandoptimization,clocktreesynthesis,routing,manufacturability,andlow-powercapabilitiesthatenabledesignerstoimplementtoday’shigh-performance,complexdesignsonschedule.ICCompileroverviewComprehensivePlaceandRouteSystem•Multicoresupportforhigherthroughputfordesignsinmainstreamsilicontechnologies•Highperformanceforadvancedsilicontechnologies•Comprehensiveoptimizationcapabilitiesmeettiming,area,power,signalintegrity,routabilityandmanufacturingobjectives•Predictabilityduringtheimplementationprocess•Singletimer•Completenetlist-to-GDSIIsolutionforbestQoRandTTRICCadvancedfeaturesThetypicalflowoftheICdesignandPhysicalimplementationTheICdesignRoadmapSYNOPSYSflowtoolsUsagemapThePartitionflowInCadencetoolsThegeneralflowofICCP&RDatasetupfloorplanningplacementCTSRoutingChipFinishing/ExportNetlistSDCUPFtechfile.dbSetuptheVirableTarget_libraryLink_libraryRefrence_libraryandcreatetheMilkywaylibrary,readintheverilognetlistandlinkthedesignwiththe.dbLoadtheUPFafterthenetlistreadCreate_mw_libRead_verilogLoad_upfLink-forceSet_min_librarySet_operating_conditionsSet_tlu_plus_filesCheck_mv_designThegeneralflowofICCfloorplanDatasetupfloorplanningplacementCTSRoutingChipFinishing/ExportNetlistSDCUPFtechfile.dbCreate_floorplanThenforgroupsCreate_plan_groupsCreate_fp_plan_group_paddingCreate_fp_placementShape_fp_blocksCommit_fp_plan_groupsCreate_power_strapsAdd_tap_cell_arrayIfLOW_POWERenabledthenCreate_voltage_areaAdd_power_switchDerive_pg_connectionPreroute_standard_cellsThegeneralflowofICCplace_optDatasetupfloorplanningplacementCTSRoutingChipFinishing/ExportNetlistSDCUPFtechfile.dbSource$SDCSet_host_options–max_cores6Place_opt-efforthigh–congestion–power–area_recoveryPsynopt-area_recovery–power-congestionThegeneralflowofICCCTSDatasetupfloorplanningplacementCTSRoutingChipFinishing/ExportNetlistSDCUPFtechfile.dbRemove_clock_treeSet_delay_calculationDefine_routing_ruleSet_clock_tree_referenceSet_clock_tree_optionsSet_ignored_layer–maxMetal6Clock_opt-only_cts-no_clock_routeSet_propagated_clock[get_clocks*]Extract_rc-estimatePsynopt–congestion–area_recoveryThegeneralflowofICCRouteDatasetupfloorplanningplacementCTSRoutingChipFinishing/ExportNetlistSDCUPFtechfile.dbSet_si_optionsSet_route_mode_optionsSet_route_zrt_detail_optionsSource${antenna_rule}Route_zrt_group-all_clock_netsExtact_rcRoute_opt–efforthigh–xtalk–powerInsert_zrt_redundant_viasInsert_stdcell_fillerVerify_zrt_routeRoute_zrt_ecoThegeneralflowofICCexportDatasetupfloorplanningplacementCTSRoutingChipFinishing/ExportNetlistSDCUPFtechfile.dbChange_names–rulesverilog-hierWrite_verilogSet_write_stream_optionsWrite_streamICCfloorplanmethodICCEncounterDEFTheDEFexchangeflooplanandPrerouteinformationonlysavetimeforEditPower,lessiterationtherebetweentoolsSolvethediscrepancybetweenICCandencounterWhenwestarttheplace_optinICC_shell,weneedaddthecommandbelowhere,thiscommandforcethepreroutetobedon’ttouchset_attribute\[get_net_shape-f“route_type==signal_route”]route_typeuser_enterPhysicalVerificationtoolsofCalibre•Calibre'sphysicalverificationcapabilitiesaretheindustrystandardforaccuracy,reliability,andperformance.•Calibre®nmDRCandCalibrenmLVSarethemarketshareleadersinphysicalverification.•CalibrealsoleadsthemarketwithinnovativefeaturessuchasincrementalDRC,whichensuresyoucancompleteyourdesignrulecheckingquicklyandefficiently,andequation-baseddesignrules,whichletdesignersdefinecontinuous,three-dimensionalfunctionsthataccuratelyandpreciselyreflectthecomplexphysicalinteractionsoftoday'snanometerdesigns.LayoutverificationafterICC•TheLVScalibreflowintroduction•TheDRCcalibreflowintroductionTheoutputfromICCafterchipfinish2019/12/2420DRCrunsetexample•command：calibre-drc-hierrunset•Thedetailreportisin:DRC.rep2019/12/2421CalibreLVSrunsetexample•v2lvs-vMY_CHIP_LVS.v-ltsmc18_lvs.v-oMY_CHIP_PAD.spi-stsmc18_lvs.spi•V2lvstransferNetlisttoSpiceNetlist•calibre-lvs-spicelayout.spi-hier-autoRUNSETPrimeTimeoverview•TheSynopsysPrimeTimesuiteincludesPrimeTime,PrimeTimeSI,PrimeTimePXandPrimeTimeVX.•Anchoredbythemosttrustedandadvancedstatictimingsignoffsolutionforgate-leveldesigns,thePrimeTimesuiteofferscomprehensivesignalintegrityanalysis,statisticaltiminganalysisandfullchippoweranalysisinasingleintegratedenvironment.KeybenefitsofPrimeTime•HSPICE-AccurateResultsMinimizeOver-Design•IntegratedDesignEnvironmentImprovesProductivity•FastTurn-aroundTimeSpeedsAnalysisandSignoff•HighCapacityApproachReducesHardwareCosts•CompleteSolutionEnsuresComprehensiveSignoffPrimeTimeSTAflowuse.sdfPrimeTimeE