1组合逻辑电路习题课2一、组合逻辑电路的基本概念1.定义2.结构特点(1)电路由逻辑门构成,不含记忆元件;(2)输入信号是单向传输的,电路中不含反馈回路;3.功能描述真值表;表达式;卡诺图;电路图;波形图3二、SSI构成的组合逻辑电路的分析和设计1.分析步骤(1)从输入端开始,逐级推导出函数表达式;(2)列真值表(3)确定逻辑功能2.设计步骤(1)列真值表;(2)写最简表达式;(3)画逻辑电路4三、MSI组合逻辑电路的工作原理及应用1.功能表、简化逻辑符号2.典型应用(1)用二进制译码器设计组合逻辑电路(2)用数据选择器设计组合逻辑电路四、组合逻辑电路中的竞争和冒险1.竞争和冒险的概念(1)1型冒险和0型冒险;(2)逻辑冒险和功能冒险;52.逻辑冒险、功能冒险的检查3.冒险的消除方法五、例题讲解6例1:分析下图电路的逻辑功能。4位加法器4位数值比较器B3A3B2A2B1A1B0A01001D3D2D1D00(AB)i(A=B)i(AB)iF(AB)F(A=B)F(AB)74851A3A2A1A0B3B2B1B0S3S2S1S0Y3Y2Y1Y0CI0COCO074LS28307D3D2D1D0Y3Y2Y1Y0CO000000000000100010001000100001100110010001000010101010011001100011101110100010000100110010101000001101100011110000101110100111111001001111101011解:①逻辑真值表②分析:当D3~D0≤9时,F(AB)=0,Y3~Y0等于D3~D0,即为十进制数的0~9;当D3~D0>9时,F(AB)=1,则加法器将D3~D0加上6,Y3~Y0就等于调整后的十进制数的个位,同时CO=1表示十进制数的十位。③结论:此电路是将4位二进制数D3~D0转化为十进制数的8421BCD码的电路。8例2:试用4位超前进位加法器74LS283构成4位减法器。解:设被减数为A3A2A1A0,减数为B3B2B1B0。由二进制运算法则可知,A3A2A1A0减去B3B2B1B0等于A3A2A1A0加上B3B2B1B0的补码。而补码等于反码加1。故B3B2B1B0的补码可以利用非门求B3B2B1B0的反码,利用低位进位输入端CI接1实现B3B2B1B0的反码加1。1A3A2A1A0B3B0B1B2CICO74LS283S3S2S1S01A3A2A1A0B3B2B1B0111S3S2S1S094.1分析图P4.1电路的逻辑功能10解:(1)推导输出表达式Y2=X2;Y1=X1X2;Y0=(MY1+X1M)X0(2)列真值表MX2X1X0Y2Y1Y0000000010010001101000101011001111000100110101011110011011110111100000101101011011110110000000101101011111010010111(3)逻辑功能:当M=0时,实现3位自然二进制码转换成3位循环码。当M=1时,实现3位循环码转换成3位自然二进制码。12图P4.2123456ABCD654321DCBATitleNumberRevisionSizeBDate:3-Mar-2002SheetofFile:E:\DesignExplorer99SE\Library\YangHengXin\MyDesign.ddbDrawnBy:=1=11&&1BCAFF124.2分析图P4.2电路的逻辑功能。13解:(1)从输入端开始,逐级推导出函数表达式F1=A⊕B⊕CF2=A(B⊕C)+BC=ABC+ABC+ABC+ABC(2)列真值表14ABCF1F20000000111010110110110010101001100011111(3)确定逻辑功能假设变量A、B、C和函数F1、F2均表示一位二进制数,那么,由真值表可知,该电路实现了全减器的功能。15A、B、C、F1、F2分别表示被减数、减数、来自低位的借位、本位差、本位向高位的借位。ABCF1F2-被减数减数借位差164.4设ABCD是一个8421BCD码,试用最少与非门设计一个能判断该8421BCD码是否大于等于5的电路,该数大于等于5,F=1;否则为0。解:(1)列真值表17ABCDF0000000010001000011001000010110110101111ABCDF10001100111010Ø1011Ø1100Ø1101Ø1110Ø1111Ø18(3)画逻辑电路,如下图所示:(2)写最简表达式ABCDØØ1110ØØØØ11111010010110100F=A+BD+BC=A·BD·BC19123456ABCD654321DCBATitleNumberRevisionSizeBDate:3-Mar-2002SheetofFile:E:\DesignExplorer99SE\Library\YangHengXin\MyDesign.ddbDrawnBy:&&&DBCAF&题4.4图204.10电话室对3种电话编码控制,按紧急次序排列优先权高低是:火警电话、急救电话、普通电话,分别编码为11,10,01。试设计该编码电路。解:设火警为A,急救为B,普通为C,列真值表为:111001ABCF1F2101001000210001111001111111ABCF1=A+B000111100111111ABCF2=BA224.11试将2/4译码器扩展成4/16译码器A1ENY3A02/4Y2译码器Y1Y0ENA12/4(1)A0Y0Y1Y2Y3ENA12/4(2)A0Y0Y1Y2Y3ENA12/4(3)A0Y0Y1Y2Y3ENA12/4(4)A0Y0Y1Y2Y3A3A2A1A0Y0Y1Y2Y3Y4Y5Y6Y7Y8Y9Y10Y11Y12Y13Y14Y15234.12试用74138设计一个多输出组合网络,它的输入是4位二进制码ABCD,输出为:F1:ABCD是4的倍数。F2:ABCD比2大。F3:ABCD在8~11之间。F4:ABCD不等于0。24解:由题意,各函数是4变量函数,故须将74138扩展为4-16线译码器,让A、B、C、D分别接4-16线译码器的地址端A3、A2、A1、A0,可写出各函数的表达式如下:)12,8,4,0(),,,(1mDCBAF=m0m4m8m12=Y0Y4Y8Y1225)11,10,9,8(),,,(3mDCBAF04),,,(mDCBAF=m8m9m10m11)2,1,0(),,,(2mDCBAF=m0m1m2=Y0Y1Y2=Y8Y9Y10Y11=Y026实现电路如下图所示:123456ABCD654321DCBATitleNumberRevisionSizeBDate:4-Mar-2002SheetofFile:E:\DesignExplorer99SE\Library\YangHengXin\MyDesign.ddbDrawnBy:YYYYYYYYAAAEEE0112A012345677413822BYYYYYYYYAAAEEE0112A012345677413822B&&&0001ABCDF1F2F3F4274.13试将八选一MUX扩展成三十二选一MUX。ENA2A1A0D0D174151(1)YD2D3D4D5D6D7ENA2A1A0D0D174151(8)YD2D3D4D5D6D71A2Y0A1Y1A0Y274138Y3E1Y4E2AY5E2BY6Y7100A5A4A3A2A1A0D0D1D7D56D57D63Y0Y7Y284.14试用74151实现下列函数:。)7,4,2,1(),,,()1(mDCBAF。)8,7()14,13,12,3,0(),,,()4(mDCBAF解:(1)函数有4个输入变量,而74151的地址端只有3个,即A2、A1、A0,故须对函数的卡诺图进行降维,即降为3维。2910111101110010110100ABCD00001DDDD010110100ABCD6D7D5D41D2D3D1D0010110100A2A1A0D0=D3=D,D1=D2=D,D4=D5=D6=D7=0令A=A2、B=A1、C=A0则:30相应的电路图如下所示:123456ABCD654321DCBATitleNumberRevisionSizeBDate:4-Mar-2002SheetofFile:E:\DesignExplorer99SE\Library\YangHengXin\MyDesign.ddbDrawnBy:DDDD013412D74151DAAA20ENY567DDABCFDD31(4)函数有4个输入变量,而74151的地址端只有3个,即A2、A1、A0,故须对函数的卡诺图进行降维,即降为3维。Ø1011111Ø01110010110100ABCDD6D7D5D41D2D3D1D0010110100A2A1A01D00100DD010110100ABC32D0=D7=D,D1=D,D2=D3=D4=D5=0。D6=1,相应的电路图如右图所示:123456ABCD654321DCBATitleNumberRevisionSizeBDate:4-Mar-2002SheetofFile:E:\DesignExplorer99SE\Library\YangHengXin\MyDesign.ddbDrawnBy:DDDD013412D74151DAAA20ENY567DDABCFDDD14.14(4)令A=A2、B=A1、C=A0则:334.15用½74153实现下列函数:。)15,7,4,2,1(),,,()1(mDCBAF解:(1)函数有4个输入变量,而½74153的地址端只有2个,即A1、A0,故须对函数的卡诺图进行降维,即降为2维。34101111101110010110100ABCD0C⊕D0C⊙D0CD11ABD2D00D10D311A1A00D001DDDD010110100ABC35D0=C⊕D,D1=C⊙D,D2=0,D3=CD,令A=A1、B=A0,则:相应的电路图如下图所示:123456ABCD654321DCBATitleNumberRevisionSizeBDate:5-Mar-2002SheetofFile:E:\DesignExplorer99SE\Library\YangHengXin\MyDesign.ddbDrawnBy:YAADENDD012301D7415312_AB=1=&FCD364.16试在图4.2.31的基础上增加一片7485,构成25位数据比较器。=A3A2A1A0B3B2B1B0(AB)i(A=B)i7485(1)(AB)iFABFA=BFABA20B20A24A23A22A21B24B23B22B21=A5B5A9A8A7A6B9B8B7B6=A0B0A4A3A2A1B4B3B2B1=A10B10A14A13A12A11B14B13B12B11=A15B15A19A18A17A16B19B18B17B16FABFA=BFABA3A2A1A0B3B2B1B0(AB)i(A=B)i7485(2)(AB)iFABFA=BFABA3A2A1A0B3B2B1B0(AB)i(A=B)i7485(3)(AB)iFABFA=BFABA3A2A1A0B3B2B1B0(AB)i(A=B)i7485(4)(AB)iFABFA=BFABA3A2A1A0B3B2B1B0(AB)i(A=B)i7485(6)(AB)iFABFA=BFABA3A2A1A0B3B2B1B0(AB)i(A=B)i7485(5)(AB)iFABFA=BFAB374.17设A