ARM内核结构简介

ARM‹™™MMU™ARM™THUMB™™™ARM32THUMB16™BXRm*ARM™BigEndianformat0x1234567812345678™LittleEndianformat0x1234567878563412™81632™ARM37™3132™632ARMARM™¾R0~R7¾R8~R14¾(PC)R15™CPSRSPSR_fiqCPSRR15(PC)R14_fiqR13_fiqR12_fiq….R8_fiqR7…R1R0SPSR_svcCPSRR15(PC)R14_svcR13_svcR12….R8R7…R1R0SPSR_abtCPSRR15(PC)R14_abtR13_abtR12….R8R7…R1R0SPSR_irqCPSRR15(PC)R14_irqR13_irqR12….R8R7…R1R0CPSRR15(PC)R14R13R12….R8R7…R1R0SPR13LRPCARMARMARM0x00x20ARM00ROM……………………0x000000000xFFFFFFFFMMU™3232™™ARM7TDMIMMU™ARM™™™32RISC(ReducedInstructionSetComputer)™/32™™Pipeline:3forARM7,5forARM9ARMADDEQR0,R1,R2LSL#3;IftheZflagisset,thendoa;multiplyR2by2^3followedbyan;addofR1andstoreresultintoR0ARM™™™™™™™SWI™™™™IO™/™THUMB16“Thumb”ARM65%16ARM160%Thumb:.256byte,4K(ARM32Mbytes)(ARM)10%THUMBThumbBNElabel;skipnexttwoinstructionsifZflagis0LSLR2,R2,#3;multiplyR2by2^3andplaceinR2ADDR0,R1,R2;addR1+R2andplaceinR0:label;continueThumb™™™™™™ADR™ADRL™LDR™ALIGN™DCx™EQUx™OPT™JTAGTMSTCKTDITDOnTRSTARM7TDMI™ICE-RTARM7TDMI•ARMExceptionHandler–Reset–Undefinedinstruction–SWI–Prefetchabort–Dataabort–Reserved–FIQ–IRQRESET•reset–ENTRY–0x04Byte,EA0000XX–CPSR–BSP–CUndefinedInstruction•––0x4,4bytes–Donothing–SWI•–0x8,4Bytes–monitor––ARMThumbAbort•Perfectabort––0x0c,4bytes•Dataabort––0x10,4bytes–donothing–FIQIRQ•FIQ–0x18,4bytes•IRQ–0x1c,4bytes–FIQIRQ–IRQFIQ–