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西南交通大学本科毕业设计(论文)第V页摘要先进的数字系统为实现高速算术运算都包含有乘法器电路，通常乘法器处于关键延时路径上，因此乘法器的速度对整个系统性能有重要影响。高速，低功耗,版图规则和占用较少的面积是目前乘法器的设计目标。通常乘法器速度取决于算法及结构。乘法器按结构可分为串行（阵列）乘法器和并行乘法器，串行乘法器面积和功耗最小，但是运算速度也最慢，因此高速数字应用系统通常会采用并行乘法器。本文通过对移位相加串行阵列乘法器和并行阵列乘法器工作原理的深入分析，设计出了4X4位的串行乘法器和4X4位并行乘法器，对它们的延时，面积等参数进行了比较，并对所设计电路的版图仿真。经过对比2种乘法器的性能，确定并行乘法器比串行乘法器的性能优越，因此高速数字应用系统通常会采用并行乘法器。在并行乘法器结构基础上，采用层次化设计方式设计出无符号8X8位并行乘法器；在无符号8X8位并行乘法器基础上，设计了符号位扩展，完成了带符号位8X8位并行乘法器的原理图设计、版图设计和后端仿真，并给出了带有延时参数的仿真波形图。完通过对8X8位并行乘法器结构的分析研究，对带符号8X8并行乘法器设计进行了优化，并完成了优化后带符号8X8并行乘法器的原理图设计、版图设计和后端仿真，经过对比优化前后带符号8X8并行乘法器的运算速度、面积等参数，并比较版图仿真的延时参数，确定经过优化的乘法器性能比优化前更优秀。关键词：数字乘法器；并行乘法器；串行乘法器；加法器阵列西南交通大学本科毕业设计(论文)第VII页AbstractWiththefastdevelopmentofintegratecircuittechnology,theuseofpowerfulEDAtoolsinthedigitaldesignisneededwhilethescaleandthecomplexofdesignhasincreasedincessant,alsothedesigncycleisshorted.Especiallythemicron-electronicswithdeep-inferiormicron,theintegrationdegreeofthesingleslicecanbereachedtomillionstransistor,thechangeoftechnologyhasagreateffectwiththechips,evenwiththesuccessorfailofsystemdesign.ThispaperismainlyabouthowtousethecadenceEDAtoolswhichdevelopedwiththecompanyofcadencetodesignaCMOSDigitalMultiplier.Inthispaperismainlyintroducedthemainprincipleofthedigitalarraymultiplieranddiscussedtheadvantageofeachother.Then4X4bitserialmultiplierand4X4bitparallelmultiplierhavebeendesigned,wediscussedthedelayandtheareaofbothmultiplier.Withthestimulateofthelayoutofboth4X4bitmultipliers,inprovedthatthe4X4bitparallelmultiplierismuchspeederthan4X4bitserialmultiplier,sotheparallelmultiplierisalwaysusedinthehighspeeddigitalapplicationsystem.Putforwardthedesignof8X8bitparallelmultiplierwhichbasedontheadministrativelevels.Designedthesignbitextensionandfinishedtheschematic,layoutandstimulationwithlayoutof8X8bitparallelmultiplierwithsignbitextension.Thestimulationwaveisshownwithdelayparameter.Putforwardthedesignofoptimized8X8bitparallelmultiplier,optimizedtheolddesignof8X8bitparallelmultiplierwithsignbitextensionandfinisheditsschematic,layoutandstimulationoflayout.Andhaveacomperationofthespeedandusedareabetweenoptimizedmultiplierwitholddesign.Withtheresultparameterofstimulationoflayout,improvedthattheoptimizedparallelmultiplierismuchspeedandlessareathanolddesign.keywords：Digitalmultiplier；parallelmultiplier；serialmultiplier；arrayadder西南交通大学本科毕业设计(论文)第VIII页目录摘要................................................................VABSTRACT.............................................................VII第1章乘法器与EDA工具概述...........................................11.1乘法器分类..........................................................................................................................................11.2EDA工具概述.......................................................................................................................................21.3本文的主要内容....................................................................................................................................5第2章乘法器设计方案选择比较.........................................62.1串行阵列乘法器....................................................................................................................................72.2并行乘法器原理....................................................................................................................................82.2.1并行阵列乘法器...........................................................................................................................82.2.2Wallace乘法器..........................................................................................................................102.2.3Booth乘法器..............................................................................................................................102.2.4ModifyBooth-Wallace乘法器................................................................................................11第3章乘法器基本单元设计.............................................123.1二输入异或门设计和仿真..................................................................................................................123.2一位全加器设计和仿真......................................................................................................................153.3一位半加器的设计与仿真..................................................................................................................22第4章四位乘法器的设计...............................................254.1四位串行乘法器的设计......................................................................................................................254.2四位并行乘法器的设计......................................................................................................................29第5章基于层次化设计的8位并行乘法器的设计...........错误!未定义书签。5.1输入模块的设计.....................................................................................................错误!未定义书签。5.2两位乘法器模块的设计.........................................................................................错误!未定义书签。5.3四位乘法器模块的设计.........................................................................................错误!未定义书签。5.4进