Xilinx-Spartan-3AN-开发板原理图

Spartan-3A/3ANStarterKitBoardSchematic(Annotated)21-AUG-2007Foradditionalinformation…:Spartan-3A/3ANStarterKitUserGuideforfurtherinformationoneachboardfeatureSpartan-3A/3ANStarterKitBoardTMFX2ExpansionConnector,6-pinHeadersHiroseFX2100-pinExpansionConnectorConnectorlessDebuggingPortLandingPadsSix-pinAccesoryHeadersDACAnalogOutputsADCAnalogInputsFX2ExpansionConnectorSix-pinAccessoryHeadersConnectorlessDebuggingPortADCInputsDACOutputsSpartan-3A/3ANStarterKitBoardTMRS-232,VGA,Audioports,SMAconnectorStereoAudiominijackPS/2Mouse/KeyboardconnectorClockInput/OutputSMAconnectorRS-232serialports12-bitVGAportSPIPROMselectjumpersVGAPS/2AudiojackClockSMASPIselectjumperRS-232DCEDTEThePS/2connectorhasprimaryandsecondaryconnectionstotheFPGA.ThesecondaryconnectionsareavailablebyattachinganexternalY-splittercable.PrimaryDATASecondaryDATAPrimaryCLKSecondaryCLKNOTE:SeeschematicPage13fordetails.Spartan-3A/3ANStarterKitBoardTM10/100EthernetPHY,magneticsRJ-45ConnectorLAN870010/100EthernetPHY(1.2V)(3.3V)(3.3V)(1.8V)FPGAFPGADDR2SDRAMTermination(0.9V)DDR2SDRAMDevice,FPGA(1.8V)DACReferenceVoltage(3.3V)DDR2SDRAMVoltageRef.(0.9V)ICInterface2ICInterface2regulatorsPowerswitchWallpoweradapterinputI/OBank3Spartan-3A/3ANStarterKitBoardTMConfiguration,Modepins,PlatformFlashPROMSUSPENDpin,JTAGheaderSecond4MbitPlatformFlashPROMisnotmountedPlatformFlashEnableFPGAModeSelectjumperJTAGHeaderPlatformFlashPROMFPGAConfigurationControlSUSPENDslideswitchPROG_BjumperDONELEDDONELEDPROG_BpushbuttonPROG_BpushbuttonSUSPENDswitchJTAGHeaderPlatformFlashPROM(JumperJ26)M0M1M2J26MasterSerialM0M1M2J26MasterSPIM0M1M2J26MasterBPIM0M1M2J26JTAGM0M1M2J26MasterInternalSPIPlatformFlashEnableJumper(JumperJ46)(Spartan-3ANonly)DONECEGNDJ46PROMDONECEGNDJ46PROMDONECEGNDJ46PROMPlatformFlashEnableJumper(JumperJ46)DISABLEEnableonlyduringconfigurationEnableAlwaysAlsoenablePlatformFlashPROMusingJumperJ46DisablePlatformFlashPROMbyremovingJumperJ46(JumperJ46)Spartan-3A/3ANStarterKitBoardTMFPGAI/OBank0andBank1,ClockOscillators50MHzOscillatorAuxiliaryOscillatorSocketCLK_50MHZCLK_AUXFPGABank1FPGABank0FPGA:XC3S700A/AN-4FGG484C(EFPGA:XC3S700A/AN-4FGG484C(ES)Spartan-3A/ANStarterKitBoardTMFPGAI/OBank2andBank3FPGAFPGABank2Bank3AWAKELEDFPGAI/OBank3isdedicatedtotheDDR2SDRAMinterfaceinterfaceFPGA:XC3S700A/AN-4FGG484C(ES)FPGA:XC3S700A/AN-4FGG484C(ES)Spartan-3A/3ANStarterKitBoardTMFPGAPowerSupplyDecouplingSpartan-3A/3ANStarterKitBoardTMADC,DAC,andPre-amplifier(ADC)LTC1407-1,two-channel,12-bitresolution,serial=H0,C1,C1155,C1001,C1158,P2484Digital-to-AnalogConverter(DAC)LTC2624,four-channel,12-bitresolution,serial=H0,C1,C1155,C1005,C1156,P2048(3.3V)(nominally3.3V)TheDAC_REF_CDvoltageisprogrammableviatheI2CcontrolinterfaceontheLP3906voltageregulatordesignatedasIC18onsheet5.Atpower-up,thisreferencevoltageis3.3V.(seesheet2)Theveninterminationtoimprovethesignalintegrityonthesehigh-fanoutsignals.ProgrammableGainAmplifier(AMP)LTC6912-1,two-channel,serial=H0,C1,C1154,C1009,C1121,P75960ΩSpartan-3A/3ANStarterKitBoardTM32Mx16DDR2SDRAM32Mx16DDR2SDRAMDDR2SDRAMdeviceTerminationnetworkConnectstoFPGAI/OBank3TheDDR2SDRAMinterfacehasspecificpinassignmentandlayoutrequirementstosupporttheXilinxMemoryInterfaceGenerator(MIG)software.Seethe“DDRSDRAM”chapterinUG334:Spartan-3A/3ANStarterKitUserGuide.0ΩDESIGNNOTE:TheRevisionCboardhasaninductorinthislocation.Shortingacrossthislocationimproveshigh-frequencyDDR2SDRAMinterfaceperformance.TheRevisionDboardusesa0Ωresistor.DESIGNNOTE:TheRevisionCboardhasaninductorinthislocation.Shortingacrossthislocationimproveshigh-frequencyDDR2SDRAMinterfaceperformance.TheRevisionDboardusesa0Ωresistor.Spartan-3A/3ANStarterKitBoardTMM29DW323DTx8/x16ParallelNORFlashSTMicroelectronicsM29DW323DT32Mbit,x8/x16parallelNORFlash®AtmelDataFlashSTMicroSPIFlashSPIFlashselectjumpers(JumperJ1)J1J1DONECEGNDJ46PROMPlatformFlashJumper(JumperJ46)JumperJ1defineswhichSPIFlashisusedforSPImodeconfigur