搜索
RevisionDateChangeDescriptionAuthorApprovedbyDocumentRevisionHistoryREV:B2DF(AI)DF(SMT)DF(Soldering)DF(Process)DF(Test)DF(Reliability)10%10%20%30%20%10%EVT60#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!DVT80#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!P/R90#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!#DIV/0!ProjectQ'ty提案件数CloseRate结案率Green:OKfornextbuild0#DIV/0!0#DIV/0!Yellow:Correctiveactionmustbeimplementedbynextbuild.0#DIV/0!0#DIV/0!Red:StopNextbuilduntilcorrectiveactionisimplemented.0#DIV/0!0#DIV/0!Item项目CloseQ'ty结案件数Issue_AI&SMT0DesignForManufacturingReviewList生产易制性问题确认查检表ColorTable:Green:OKfornextbuildYellow:Correctiveactionmustbeimplementedbynextbuild.Red:StopNextbuilduntilcorrectiveactionisimplemented.DFXScore易制性评分Judgement判定Total0CustomerProject客户机种中磊Stage阶段Limit(=)界线Modelname机种名称AM12W-120C-RIssueTE0IssueQE0IssueSME0IssueIE0020406080100EVTDVTP/RDFXScoreCardLimit(=)界线DFXScore易制性评分TotalDFAIPossiblePointsTotalDFAICompliancePoints(EVT)Score(EVT)TotalDFAICompliancePoints(DVT)Score(DVT)TotalDFAICompliancePoints(P/R)Score(P/R)00#DIV/0!0#DIV/0!0#DIV/0!ItemDFAIRequirementsPriorityLevel(1,2,3,NA)MaxPointsAvailableDFAIPoints(5,3,1,0)(EVT)DFAIPoints(5,3,1,0)(DVT）DFAIPoints(5,3,1,0)（P/R)DFAICompliance(Y,N,NA)Comments(AccordingtoList)1极性元件标示明确且正确,以利贴装方向正确FALSEFALSEY2OSP单面PCB是密封或真空包装OSPSinglePCBforvacuumpackage.FALSEFALSEY3PCB连板设计已考虑潜在的过炉变形隐患DesignPWBpanelhavenotpotentialwarpwhenthroughthereflow.FALSEFALSEY4AI相邻元件间,后插元件时刀具不压伤先插元件脚.参考距离1.8mm*IfAIborderuponcomponentgapisshortage,Devicecutterwillpressdowncomponentwirelead.FALSEFALSEY5AI相邻元件本体间有间隙﹐没有相互踫触.Atleast0.5mmgapbetweenborderuponcomponentbody.FALSEFALSEY6卧式元件植件LayoutPitch为5~25mm.AIcomponentlayoutpitchfromMin6mmtoMax25mm.FALSEFALSEY7卧式元件植件LayoutPitch≧(元件本体长度+元件脚径+1.6mm).FALSEFALSEY8卧式元件来料包装方式均为带状.且材料均符合规格要求.AIcomponentpackagefortapemeetspecforDesignGuidelin*FALSEFALSEY9卧式元件脚长度在1.80mm以内,且不会阻挡RI剪切刀具造成RI元件脚长.AIcomponentleadlengthMax1.8mmapprovePanasonicdeviceinsertion.FALSEFALSEY10卧式元件脚长度在1.80mm以内,且不会阻挡SMD点胶动作或连锡短路.Axiscomponentleadhaven`tblocknozzleofSMDwhenleadlengthismax.1.8mm.FALSEFALSEY11卧式元件脚径与PCB孔径相匹配(脚径+0.4mm(或0.3mm)=PCB孔径).AxiscomponentleaddiameterapprovetheirPWBholesize.FALSEFALSEY12卧式元件脚径≧0.4mm而≦0.8mm.Axiscomponentleaddiameterdefineform0.4mmto0.8mmbyMachineinsertion.FALSEFALSEY13卧式元件的植件位置均为90度,180度﹔Axiscomponentinsertionangleforonly90or180degree.FALSEFALSEY14RI相邻元件本体间间隙大于0.5mm.（并考量零件本体的公差都在上限时).RadialInsertioncomponentbodyborderupongapatleast0.5mm(componentbodydimetertoleranceatupper).FALSEFALSEY15立式元件脚长度在1.80mm时,过锡炉后不会相互连锡短路(距离0.8mm).NoshortandbridgeafterwavesolderwhenRIcomponentwireleadat1.8mm.FALSEFALSEY16立式元件植件LayoutPitch均为2.5mm/5.0mm(最佳),特殊7.5mm.FALSEFALSEY17立式元件脚长度在1.80mm时,不会阻挡SMD点胶动作.NoblocknozzleofSMDdevicedispenserwhenRIcomp.Wireleadat1.80mm.FALSEFALSEY18PCB上定位孔(左)直径为4.0(0~0.1)mm且其孔中心到PCB边缘距离为5.0±0.1mm.PCBpositionholediameteris4.0(0-0.1)mmandthedistancefromtheholecentertopcboutsideedgeis5.0±0.1mm.FALSEFALSEY19立式元件来料包装方式均为带状.(特殊情况除外)OnlytapepackageforPanasonicRIdevice.FALSEFALSEY20设计造成PCB上凸与下凹弯曲程度不超出1.2mm而影响设备植件.PWBwarplimit:lessthan+1.2mm.FALSEFALSEY21设计的PCB联板在制程中不会造成变形或边条断裂Nopotentialwarpandpaneledgebreakinallofprocess.FALSEFALSEY22自动插件两卧式零件(孔径中心)相距2.5mm；(Thepitchis2.5mmintwoauto-insertionpart.)FALSEFALSEY23RI元件脚径大于等于0.8mm材质不可用铁脚,否则不能RHFALSE0ND9脚径为1.0mm,不适合RHDesignforAutoInsertionScoreCard回主页24AI元件本体直径不能大于6mm,本体长度不能大于14mmFALSEFALSEY25RH元件高度:＜21mm(插入后元件本体顶部与PCB平面间距)元件直径:＜13mmFALSEFALSEY26RH件孔与周边AI/RH件之间距离要保持3.5mm以上距离FALSEFALSEY27AI件孔与周边SMD件之间距离要保持2.7mm以上距离FALSEFALSEY28固态电容非k脚不能自插,否则会拉伤NA0NATotalDFSMTPossiblePointsTotalDFSMTCompliancePoints(EVT)Score(EVT)TotalDFSMTCompliancePoints(DVT)Score(DVT)TotalDFSMTCompliancePoints(P/R)Score(P/R)00#DIV/0!0#DIV/0!0#DIV/0!ItemDFSMTRequirementsPriorityLevel(1,2,3,NA)MaxPointsAvailableDFSMTPoints(5,3,1,0)(EVT)DFSMTPoints(5,3,1,0)DFSMTPoints(5,3,1,0)(P/R)DFSMTCompliance(Y,N,NA)Comments(AccordingtoList)1极性元件标示明确且正确,以利贴装方向正确FALSEFALSEY2OSP单面PCB是密封包装OSPSinglePCBforvacuumpackage.FALSEFALSEY3有连板设计不存在的过炉后变形隐患DesignPWBpanelhavenotpotentialwarpwhenthroughthereflow.(referenceDesignguidelinep.66)*FALSEFALSEY4PCBpanel要有制程流向标示HaveanorientationmarkonPWBpaneledgetodirectiveprocess.FALSEFALSEY5对于贴装精度高的PCBpanel需要有定位孔。HavethepositionholeonthepaneledgefortheclosePWB.FALSEFALSEY6PCBpanel要有边条，否则PCB容易被传送轨道污染MusthavetheedgebesidePCBpaneltopreventcontaminativewhenitthroughtheSMDline.FALSEFALSEY7AI,RI,SMD元件边缘距PCB边缘应＞5.0mm(元件贴装高度大于15mm时﹐元件边缘距PCB边缘应为10mm以上),否则设备传送轨道会与元件产生磨擦，致使元件破损Thedistancehaveover5.0mmfromPWBedgetoAIRISMDcomponentlocation,andpreventfrictionandbreak(whencomponentmounthighover15mm,thedistanceover10.0mmFALSEFALSEY8SMD面PCB板上元件大小高度(max.6.5mm)要符合设备需求.Thecomponentshapesize(componenthighmax.6.50mm)approvedevicerequirement.FALSEFALSEY9SMD制程中PWB板内和板外都有FiducialMark.HavethefiducaialmarkonPWBedgeandcellboardifitwillrunSMDprocess.FALSEFALSEY10SMDFiducialMark要求周围半径2.5mm内不能有相似点(例如ICT探测点)，否则设备容易误认识，贴装坐标会整体偏移NoanalogicashapewithSMDFiducialMarkinto2.50mmradialareatopreventrecognitiondeviation.(e.g.ICTtestpo