TLV5620中文资料

TLV5620C,TLV5620IQUADRUPLE8-BITDIGITAL-TO-ANALOGCONVERTERSSLAS110B–JANUARY1995–REVISEDAPRIL19971POSTOFFICEBOX655303•DALLAS,TEXAS75265Four8-BitVoltageOutputDACs3-VSingle-SupplyOperationSerialInterfaceHigh-ImpedanceReferenceInputsProgrammablefor1or2TimesOutputRangeSimultaneousUpdateFacilityInternalPower-OnResetLow-PowerConsumptionHalf-BufferedOutputapplicationsProgrammableVoltageSourcesDigitallyControlledAmplifiers/AttenuatorsMobileCommunicationsAutomaticTestEquipmentProcessMonitoringandControlSignalSynthesisdescriptionTheTLV5620CandTLV5620Iarequadruple8-bitvoltageoutputdigital-to-analogconverters(DACs)withbufferedreferenceinputs(highimpedance).TheDACsproduceanoutputvoltagethatrangesbetweeneitheroneortwotimesthereferencevoltagesandGND;and,theDACsaremonotonic.Thedeviceissimpletouse,becauseitrunsfromasinglesupplyof3Vto3.6V.Apower-onresetfunctionisincorporatedtoensurerepeatablestart-upconditions.DigitalcontroloftheTLV5620CandTLV5620Iisoverasimplethree-wireserialbusthatisCMOScompatibleandeasilyinterfacedtoallpopularmicroprocessorandmicrocontrollerdevices.The11-bitcommandwordcompriseseightbitsofdata,twoDACselectbits,andarangebit,thelatterallowingselectionbetweenthetimes1ortimes2outputrange.TheDACregistersaredoublebuffered,allowingacompletesetofnewvaluestobewrittentothedevice,thenallDACoutputsupdatesimultaneouslythroughcontrolofLDAC.ThedigitalinputsfeatureSchmitttriggersforhighnoiseimmunity.The14-terminalsmall-outline(SO)packageallowsdigitalcontrolofanalogfunctionsinspace-criticalapplications.TheTLV5620Cischaracterizedforoperationfrom0°Cto70°C.TheTLV5620Iischaracterizedforoperationfrom–40°Cto85°C.TheTLV5620CandTLV5620Idonotrequireexternaltrimming.AVAILABLEOPTIONSPACKAGETASMALLOUTLINE(D)PLASTICDIP(N)0°Cto70°CTLV5620CDTLV5620CN–40°Cto85°CTLV5620IDTLV5620INCopyright1997,TexasInstrumentsIncorporatedPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.1234567141312111098GNDREFAREFBREFCREFDDATACLKVDDLDACDACADACBDACCDACDLOADDORNPACKAGE(TOPVIEW)TLV5620C,TLV5620IQUADRUPLE8-BITDIGITAL-TO-ANALOGCONVERTERSSLAS110B–JANUARY1995–REVISEDAPRIL19972POSTOFFICEBOX655303•DALLAS,TEXAS75265functionalblockdiagramPower-OnResetSerialInterface×2DACDAC×2×2DACDAC×2LDACREFA+–+–+–+–+–+–+–+–REFBREFCCLKREFDDATALOADDACADACBDACCDACD88888888LatchLatchLatchLatchLatchLatchLatchLatch2345768131211109TerminalFunctionsTERMINALI/ODESCRIPTIONNAMENO.I/ODESCRIPTIONCLK7ISerialinterfaceclock.TheinputdigitaldataisshiftedintotheserialinterfaceregisteronthefallingedgeoftheclockappliedtotheCLKterminal.DACA12ODACAanalogoutputDACB11ODACBanalogoutputDACC10ODACCanalogoutputDACD9ODACDanalogoutputDATA6ISerialinterfacedigitaldatainput.ThedigitalcodefortheDACisclockedintotheserialinterfaceregisterserially.Eachdatabitisclockedintotheregisteronthefallingedgeoftheclocksignal.GND1IGroundreturnandreferenceterminalLDAC13ILoadDAC.Whenthissignalishigh,noDACoutputupdatesoccurwhentheinputdigitaldataisreadintotheserialinterface.TheDACoutputsareonlyupdatedwhenLDACistakenfromhightolow.LOAD8ISerialinterfaceloadcontrol.WhentheLDACterminalislow,thefallingedgeoftheLOADsignallatchesthedigitaldataintotheoutputlatchandimmediatelyproducestheanalogvoltageattheDACoutputterminal.REFA2IReferencevoltageinputtoDACA.Thisvoltagedefinestheoutputanalogrange.REFB3IReferencevoltageinputtoDACB.Thisvoltagedefinestheanalogoutputrange.REFC4IReferencevoltageinputtoDACC.Thisvoltagedefinestheanalogoutputrange.REFD5IReferencevoltageinputtoDACD.Thisvoltagedefinestheanalogoutputrange.VDD14IPositivesupplyvoltageTLV5620C,TLV5620IQUADRUPLE8-BITDIGITAL-TO-ANALOGCONVERTERSSLAS110B–JANUARY1995–REVISEDAPRIL19973POSTOFFICEBOX655303•DALLAS,TEXAS75265detaileddescriptionTheTLV5620isimplementedusingfourresistor-stringDACs.ThecoreofeachDACisasingleresistorwith256taps,correspondingtothe256possiblecodeslistedinTable1.OneendofeachresistorstringisconnectedtoGNDandtheotherendisfedfromtheoutputofthereferenceinputbuffer.Monotonicityismaintainedbyuseoftheresistorstrings.Linearitydependsuponthematchingoftheresistorsegmentsandupontheperformanceoftheoutputbuffer.Sincetheinputsarebuffered,theDACsalwayspresentsahigh-impedanceloadtothereferencesource.EachDACoutputisbufferedbyaconfigurable-gainoutputamplifier,whichcanbeprogrammedtotimes1ortimes2gain.Onpowerup,theDACsareresettoCODE0.Eachoutputvoltageisgivenby:VO(DACA|B|C|D)REFCODE256(1RNGbitvalue)whereCODEisintherange0to255andtherange(RNG)bitisa0or1withintheserialcontrolword.Table1.IdealOutputTransferD7D6D5D4D3D2D1D0OUTPUTVOLTAGE00000000GND00000001(1/256)×REF(1+RNG)••••••••••••••••••01111111(127/256)×REF(1+RNG)10000000(128/256)×REF(1+RNG)••••••••••••••••••11111111(255/256)×REF(1+RNG)datainterfaceWithLOADhigh,dataisclockedintotheDATAterminalon