计算机组成复习重点

WilliamStallingsComputerOrganizationandArchitectureChapter1Introduction1.1Architecture&Organization1ArchitectureisthoseattributesvisibletotheprogrammerOrganizationishowfeaturesareimplemented1.2Structure&FunctionStructureisthewayinwhichcomponentsrelatetoeachotherFunctionistheoperationofindividualcomponentsaspartofthestructure1.2.1computerFunctionsAllcomputerfunctionsare:DataprocessingDatastorageDatamovementControl1.2.2StructureofdifferentlevelTopLevelComputerMainMemoryInputOutputSystemsInterconnectionPeripheralsCommunicationlinesCentralProcessingUnitComputerStructure-TheCPUComputerArithmeticandLogicUnitControlUnitInternalCPUInterconnectionRegistersCPUI/OMemorySystemBusCPUStructure-TheControlUnitCPUControlMemoryControlUnitRegistersandDecodersSequencingLogicControlUnitALURegistersInternalBusControlUnitHomework1.1Whatisthecomputerarchitecture.1.2Whatisthecomputerorganization.1.3Whatisthestructureofacomputersystem.1.4Whatarethefunctionsofacomputer.1.5Describetheprincipalelementsofacomputer.1.6DescribetheprincipalelementsofaCPU.WilliamStallingsComputerOrganizationandArchitectureChapter2ComputerEvolutionandPerformance2.vonNeumann/TuringStoredProgramconcept(1945)MainmemorystoringprogramsanddataALUoperatingonbinarydataControlunitinterpretinginstructionsfrommemoryandexecutingInputandoutputequipmentoperatedbycontrolunitStructureofvonNuemannmachineMainMemoryArithmeticandLogicUnitProgramControlUnitInputOutputEquipmentWilliamStallingsComputerOrganizationandArchitectureChapter3SystemBuses3.1ComputerComponentsThreekeyconceptsofvonNeumannarchitecture:Dataandinstructionarestoredinasingleread-writememoryMemoryareaddressableExecutioninstructionfromonetothenextFetchCycleProgramCounter(PC)holdsaddressofnextinstructiontofetchProcessorfetchesinstructionfrommemorylocationpointedtobyPCIncrementPCUnlesstoldotherwiseInstructionloadedintoInstructionRegister(IR)ProcessorinterpretsinstructionandperformsrequiredactionsInterruptCycleAddedtoinstructioncycleProcessorchecksforinterruptIndicatedbyaninterruptsignalIfnointerrupt,fetchnextinstructionIfinterruptpending:SuspendexecutionofcurrentprogramSavecontextSetPCtostartaddressofinterrupthandlerroutineProcessinterruptRestorecontextandcontinueinterruptedprogramMultipleInterruptsDisableinterruptsDefinepriorities1.WhatisaBus?AcommunicationpathwayconnectingtwoormoredevicesUsuallybroadcast3.ThreeGroupsofBusDataBusCarriesdataWidthisakeydeterminantofperformanceAddressbusIdentifythesourceordestinationofdataBuswidthdeterminesmaximummemorycapacityofsystemControlBusControlandtiminginformation5.ElementsofBusDesignBusTypeMethodofArbitrationTimingBusWidthDataTransferTypeBusTypesDedicatedMultiplexedBusArbitrationArbitrationmaybecentralisedordistributedTimingSynchronousAsynchronousWilliamStallingsComputerOrganizationandArchitectureChapter3SystemBuses3.1ComputerComponentsThreekeyconceptsofvonNeumannarchitecture:Dataandinstructionarestoredinasingleread-writememoryMemoryareaddressableExecutioninstructionfromonetothenextFetchCycleProgramCounter(PC)holdsaddressofnextinstructiontofetchProcessorfetchesinstructionfrommemorylocationpointedtobyPCIncrementPCUnlesstoldotherwiseInstructionloadedintoInstructionRegister(IR)ProcessorinterpretsinstructionandperformsrequiredactionsInterruptCycleAddedtoinstructioncycleProcessorchecksforinterruptIndicatedbyaninterruptsignalIfnointerrupt,fetchnextinstructionIfinterruptpending:SuspendexecutionofcurrentprogramSavecontextSetPCtostartaddressofinterrupthandlerroutineProcessinterruptRestorecontextandcontinueinterruptedprogramMultipleInterruptsDisableinterruptsDefinepriorities1.WhatisaBus?AcommunicationpathwayconnectingtwoormoredevicesUsuallybroadcast3.ThreeGroupsofBusDataBusCarriesdataWidthisakeydeterminantofperformanceAddressbusIdentifythesourceordestinationofdataBuswidthdeterminesmaximummemorycapacityofsystemControlBusControlandtiminginformation5.ElementsofBusDesignBusTypeMethodofArbitrationTimingBusWidthDataTransferTypeBusTypesDedicatedMultiplexedBusArbitrationArbitrationmaybecentralisedordistributedTimingSynchronousAsynchronousWilliamStallingsComputerOrganizationandArchitectureChapter4CacheChapter5InternalMemory5.OrganisationindetailMemoryorganizationhomeworkCalculateanddrawthediagram4.3Cache(Highspeedbuffer)SmallamountoffastmemorySitsbetweennormalmainmemoryandCPUMaybelocatedonCPUchipormodule1.PrincipleSmallbutfastLargebutslowCPUCacheMainMemoryWordTransferBlockTransferCacheoperation-overviewCPUrequestscontentsofmemorylocationCheckcacheforthisdataIfpresent,getfromcache(fast)Ifnotpresent,readrequiredblockfrommainmemorytocache（fixednumberofwords)ThendeliverfromcachetoCPUCacheincludestags(mark)toidentifywhichblockofmainmemoryisineachcacheslot（line）3）SetAssociativeMappingCalculateanddrawthediagramK(Two)WaySetAssociativeCacheOrganizationFindNotfindset0set1StarthereWilliamStallingsComputerOrganizationandArchitectureChapter6ExternalMemoryRAIDRedundantArrayofIndependentDisksSetofphysicaldi