半加器和全加器的设计

实验一.半加器，全加器的设计1，半加器的设计，方法一libraryieee;useieee.std_logic_1164.all;entityh_adder1isport(a,b:instd_logic;c,s:outstd_logic);endentityh_adder1;architectureoneofh_adder1isbegins=axorb;c=aandb;endarchitectureone;运行结果：方法二：运行结果：2，全加器的设计方法一：libraryieee;useieee.std_logic_1164.all;entityf_adder1isport(a,b,cin:instd_logic;sum,cout:outstd_logic);endentityf_adder1;architecturearchoff_adder1iscomponenth_adder1port(a,b:instd_logic;s,c:outstd_logic);endcomponent;componentor23port(a,b:instd_logic;c:outstd_logic);endcomponent;signalx:std_logic_vector(0to2);beginu1:h_adder1portmap(a,b,x(1),x(0));u2:h_adder1portmap(x(1),cin,sum,x(2));u3:or23portmap(a=x(0),b=x(2),c=cout);endarch;运行结果：方法二：运行结果：实验二.四选一数据选择器的设计1用case语句：libraryieee;useieee.std_logic_1164.all;entitymux4_1aisport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0));endmux4_1a;architecturearchofmux4_1aisbeginprocess(A,B,C,D,sel)begincaseseliswhen00=q=A;when01=q=B;when10=q=C;when11=q=D;whenothers=null;endcase;endprocess;endarch;运行结果：2，用if语句设计：libraryieee;useieee.std_logic_1164.all;entitymux4_1bisport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0));endmux4_1b;architecturearchofmux4_1bisbeginprocess(A,B,C,D,sel)beginIFsel=00thenq=A;elsifsel=01thenq=B;elsifsel=10thenq=C;elsifsel=11thenq=D;endifendprocess;endarch;用with语句设计：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymux4_1cisport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0));endmux4_1c;architecturearchofmux4_1cisbeginwithselselectq=Awhen00,Bwhen01,Cwhen10,Dwhen11,ZZwhenothers;endarch;运行结果：4，用when语句设计：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymux4_1disport(A,B,C,D:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);q:outstd_logic_vector(3downto0));endmux4_1d;architecturearchofmux4_1disbeginq=Awhensel=00elseBwhensel=01elseCwhensel=10elseD;endarch;运行结果：实验三,可逆计数器的设计libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydswqisport(clk,dir:instd_logic;q:bufferstd_logic_vector(3downto0));end;architecturearchofdswqisbeginprocess(clk,q,dir)beginifclk'eventandclk='1'thenifdir='0'thenq=q+1;elseq=q-1;endif;endif;endprocess;endarch;运行结果：异步清零，同步置数的同步8421BCD码计数器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount10isport(clk,r,s:instd_logic;data:instd_logic_vector(3downto0);co:outstd_logic;q:bufferstd_logic_vector(3downto0));endcount10;architecturearchofcount10isbeginco='1'when(q=1001)else'0';process(clk,r)beginif(r='0')thenq=0000;elsif(clk'eventandclk='1')thenif(s='1')thenq=data;elsif(q=9)thenq=0000;elseq=q+1;endif;endif;endprocess;endarch;运行结果：