A-Verilog-HDL-Test-Bench-Primer

AVerilogHDLTestBenchPrimerApplicationNoteiAVerilogHDLTestBenchPrimerTableofContentsIntroduction...........................................................................................................1Overview...............................................................................................................1TheDeviceUnderTest(D.U.T.)...........................................................................1TheTestBench....................................................................................................1Instantiations.........................................................................................................2Figure1-DUTInstantiation.............................................................................................2RegandWireDeclarations...................................................................................2Figure2–RegandWireDeclarations.............................................................................3InitialandAlwaysBlocks.......................................................................................3Figure3–AnInitialBlockExample...............................................................................3Figure4–AnAlwaysBlockExample............................................................................4Initialization.....................................................................................................................4Delays...............................................................................................................................4ClocksandResets............................................................................................................4AssignStatements................................................................................................4Figure5-AnAssignExample..........................................................................................5PrintingduringSimulations...................................................................................5$display............................................................................................................................5Figure6-$displayExample.............................................................................................5$monitor...........................................................................................................................5Figure7-Using$monitor.................................................................................................5Tasks....................................................................................................................6Figure8-AnExampleofaTask–load_count................................................................6Count16SimulationExample................................................................................6Table1-SimulationSteps................................................................................................6Figure9–TheTranscriptWindowfortheCount16Simulation....................................8Figure10–TheSimulationWaveformWindowfortheCount16Simulation................8GateLevelSimulations.........................................................................................9AppendixA-Thecount16.vVerilogSourceFile............................................................9AppendixB-Thecnt16_tb.vVerilogTestBenchSourceFile......................................10ReferenceMaterials............................................................................................12Publication#:AN013-1Revision:AAmendment:0IssueDate:October1999IntroductionAsdigitalsystemsbecomemorecomplex,itbecomesincreasinglyimportanttoverifythefunctionalityofadesignbeforeimplementingitinasystem.HardwareDescriptionsLanguages(HDL’s)havebecomeextremelypopularbecausethesamelanguagecanbeusedbyengineersforbothdesigningandtestingCPLD’sandFPGA’s.ThetwomostcommonHDL’sareVerilogandVHDL.ThisdocumentfocusesonusingVerilogHDLtotestdigitalsystems,bygivingthedesignerahandfulofsimulationtechniquesthatcanbeusedonthemajorityofdigitalapplications.OverviewThisapplicationsnoteandtheincludedVerilogsourcecodedescribehowtoapplystimulustoabehavioralorgateleveldescriptionofaCPLDdesign.ThedesignershouldhaveaccesstoaVerilogsimulatorandbefamiliarwithits’basicfunctionality.Inshort,theVerilogcodeforeachoftheindividualmodulesiscompiledandthesimulationisrun.Byapplyingstimulusandsimulatingthedesign,thedesignercanbesurethecorrectfunctionalityofthedesignisachieved.Thisdesignusesaloadable4-bitcounterandtestbenchtoillustratethebasicelementsofaVerilogsimulation.Thedesignisinstantiatedinatestbench,stimulusisappliedtotheinputs,andtheoutputsaremonitoredforthedesiredresults.TheDeviceUnderTest(D.U.T.)TheDeviceUnderTestcanbeabehavioralorgatelevelrepresentationofadesign.Inthisexample,theDUTisbehavioralVerilogcodefora4-bitcounterfoundinAppendixA.ThisisalsoknownasaRegisterTransferLevelorRTLdescriptionofthedesign.IntheHDLsource,alltheinputandoutputsignalsare