verilogm序列发生器

modulem_sequen(clk,rst,m_out);inputclk;inputrst;outputm_out;regm_out;reg[7:0]reg_buffer;//-------------feedback--------------//wirefeedback=reg_buffer[7]^reg_buffer[6]^reg_buffer[2]^reg_buffer[1];//----------initial,linearshifting---------//always@(posedgeclk,negedgerst)beginif(!rst)beginreg_buffer=8'b11111111;endelsebeginreg_buffer[7:0]={reg_buffer[6:0],feedback};endend//-------------checkallzero-------------//always@(posedgeclk,negedgerst)beginif(reg_buffer==8'b00000000)beginreg_buffer=8'b11111111;endend//----------------output----------------//always@(posedgeclk,negedgerst)beginif(!rst)beginm_out=1'b0;endelsebeginm_out=reg_buffer[7];endendendmodule