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-----------------------Page1-----------------------王金明：《VerilogHDL程序设计教程》【例3.1】4位全加器moduleadder4(cout,sum,ina,inb,cin);output[3:0]sum;outputcout;input[3:0]ina,inb;inputcin;assign{cout,sum}=ina+inb+cin;endmodule【例3.2】4位计数器modulecount4(out,reset,clk);output[3:0]out;inputreset,clk;reg[3:0]out;always@(posedgeclk)beginif(reset)out=0;//同步复位elseout=out+1;//计数endendmodule【例3.3】4位全加器的仿真程序`timescale1ns/1ns`includeadder4.vmoduleadder_tp;//测试模块的名字reg[3:0]a,b;//测试输入信号定义为reg型regcin;wire[3:0]sum;//测试输出信号定义为wire型wirecout;integeri,j;adder4adder(sum,cout,a,b,cin);//调用测试对象always#5cin=~cin;//设定cin的取值initialbegina=0;b=0;cin=0;for(i=1;i16;i=i+1)#10a=i;//设定a的取值end-1------------------------Page2-----------------------程序文本initialbeginfor(j=1;j16;j=j+1)#10b=j;//设定b的取值endinitial//定义结果显示格式begin$monitor($time,,,%d+%d+%b={%b,%d},a,b,cin,cout,sum);#160$finish;endendmodule【例3.4】4位计数器的仿真程序`timescale1ns/1ns`includecount4.vmodulecoun4_tp;regclk,reset;//测试输入信号定义为reg型wire[3:0]out;//测试输出信号定义为wire型parameterDELY=100;count4mycount(out,reset,clk);//调用测试对象always#(DELY/2)clk=~clk;//产生时钟波形initialbegin//激励信号定义clk=0;reset=0;#DELYreset=1;#DELYreset=0;#(DELY*20)$finish;end//定义结果显示格式initial$monitor($time,,,clk=%dreset=%dout=%d,clk,reset,out);endmodule【例3.5】“与-或-非”门电路moduleAOI(A,B,C,D,F);//模块名为AOI(端口列表A，B，C，D，F)inputA,B,C,D;//模块的输入端口为A，B，C，DoutputF;//模块的输出端口为F-2------------------------Page3-----------------------王金明：《VerilogHDL程序设计教程》wireA,B,C,D,F;//定义信号的数据类型assignF=~((A&B)|(C&D));//逻辑功能描述endmodule【例5.1】用case语句描述的4选1数据选择器modulemux4_1(out,in0,in1,in2,in3,sel);outputout;inputin0,in1,in2,in3;input[1:0]sel;regout;always@(in0orin1orin2orin3orsel)//敏感信号列表case(sel)2'b00:out=in0;2'b01:out=in1;2'b10:out=in2;2'b11:out=in3;default:out=2'bx;endcaseendmodule【例5.2】同步置数、同步清零的计数器modulecount(out,data,load,reset,clk);output[7:0]out;input[7:0]data;inputload,clk,reset;reg[7:0]out;always@(posedgeclk)//clk上升沿触发beginif(!reset)out=8'h00;//同步清0，低电平有效elseif(load)out=data;//同步预置elseout=out+1;//计数endendmodule【例5.3】用always过程语句描述的简单算术逻辑单元`defineadd3'd0`defineminus3'd1`defineband3'd2`definebor3'd3`definebnot3'd4-3------------------------Page4-----------------------程序文本modulealu(out,opcode,a,b);output[7:0]out;reg[7:0]out;input[2:0]opcode;//操作码input[7:0]a,b;//操作数always@(opcodeoraorb)//电平敏感的always块begincase(opcode)`add:out=a+b;//加操作`minus:out=a-b;//减操作`band:out=a&b;//求与`bor:out=a|b;//求或`bnot:out=~a;//求反default:out=8'hx;//未收到指令时，输出任意态endcaseendendmodule【例5.4】用initial过程语句对测试变量A、B、C赋值`timescale1ns/1nsmoduletest;regA,B,C;initialbeginA=0;B=1;C=0;#50A=1;B=0;#50A=0;C=1;#50B=1;#50B=0;C=0;#50$finish;endendmodule【例5.5】用begin-end串行块产生信号波形`timescale10ns/1nsmodulewave1;regwave;parametercycle=10;initialbegin-4------------------------Page5-----------------------王金明：《VerilogHDL程序设计教程》wave=0;#(cycle/2)wave=1;#(cycle/2)wave=0;#(cycle/2)wave=1;#(cycle/2)wave=0;#(cycle/2)wave=1;#(cycle/2)$finish;endinitial$monitor($time,,,wave=%b,wave);endmodule【例5.6】用fork-join并行块产生信号波形`timescale10ns/1nsmodulewave2;regwave;parametercycle=5;initialforkwave=0;#(cycle)wave=1;#(2*cycle)wave=0;#(3*cycle)wave=1;#(4*cycle)wave=0;#(5*cycle)wave=1;#(6*cycle)$finish;joininitial$monitor($time,,,wave=%b,wave);endmodule【例5.7】持续赋值方式定义的2选1多路选择器moduleMUX21_1(out,a,b,sel);inputa,b,sel;outputout;assignout=(sel==0)?a:b;//持续赋值，如果sel为0，则out=a；否则out=bendmodule【例5.8】阻塞赋值方式定义的2选1多路选择器moduleMUX21_2(out,a,b,sel);inputa,b,sel;-5------------------------Page6-----------------------程序文本outputout;regout;always@(aorborsel)beginif(sel==0)out=a;//阻塞赋值elseout=b;endendmodule【例5.9】非阻塞赋值modulenon_block(c,b,a,clk);outputc,b;inputclk,a;regc,b;always@(posedgeclk)beginb=a;c=b;endendmodule【例5.10】阻塞赋值moduleblock(c,b,a,clk);outputc,b;inputclk,a;regc,b;always@(posedgeclk)beginb=a;c=b;endendmodule【例5.11】模为60的BCD码加法计数器modulecount60(qout,cout,data,load,cin,reset,clk);output[7:0]qout;outputcout;input[7:0]data;inputload,cin,clk,reset;reg[7:0]qout;always@(posedgeclk)//clk上升沿时刻计数-6------------------------Page7-----------------------王金明：《VerilogHDL程序设计教程》beginif(reset)qout=0;//同步复位elseif(load)qout=data;//同步置数elseif(cin)beginif(qout[3:0]==9)//低位是否为9，是则beginqout[3:0]=0;//回0，并判断高位是否为5if(qout[7:4]==5)qout[7:4]=0;elseqout[7:4]=qout[7:4]+1;//高位不为5，则加1endelse//低位不为9，则加1qout[3:0]=qout[3:0]+1;endendassigncout=((qout==8'h59)&cin)?1:0;//产生进位输出信号endmodule【例5.12】BCD码—七段数码管显示译码器moduledecode4_7(decodeout,indec);output[6:0]decodeout;input[3:0]indec;reg[6:0]decodeout;always@(indec)begincase(indec)//用case语句进行译码4'd0:decodeout=7'b1111110;4'd1:decodeout=7'b0110000;4'd2:decodeout=7'b1101101;4'd3:decodeout=7'b1111001;4'd4:decodeout=7'b0110011;4'd5:decodeout=7'b1011011;4'd6:decodeout=7'b1011111;4'd7:decodeout=7'b1110000;4'd8:decodeout=7'b1111111;4'd9:decodeout=7'b1111011;default:decodeout=7'bx;endcaseend-7------------------------Page8-----------------------程序文本endmodule【例5.13】用casez描述的数据选择器modulemux_casez(out,a,b,c,d,select);outputout;inputa,b,c,d;input[3:0]select;regout;always@(selectoraorborcord)begincasez(select)4'b???1:out=a;4'b??1?:out=b;4'b?1??:out=c;4'b1???:out=d;endcaseendendmodule【例