eda练习题1

1、优先级编码器。图是一个7级优先级编码器。如果输入矢量中出现多个'1'，那么电路将优先对最高位编码输出。000表示输入矢量中没有出现位'1'，不需要编码输出。使用WHEN/ELSE语句实现该电路。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYencoderISPORT(x:INbit_VECTOR(7DOWNTO1);y:OUTbit_VECTOR(2DOWNTO0));ENDencoder;ARCHITECTUREencoder1OFencoderISBEGINy=111WHENx(7)=’1’ELSE110WHENx(6)=’1’ELSE101WHENx(5)=’1’ELSE100WHENx(4)=’1’ELSE011WHENx(3)=’1’ELSE010WHENx(2)=’1’ELSE001WHENx(1)=’1’ELSE000;ENDencoder1;2、编写实现如图所示状态转移关系的VHDL代码。libraryieee;useieee.std_logic_1164.all;entityfsmisport(inp,rst,clk:instd_logic;outp:outstd_logic_vector(1downto0));endfsm;architecturearchoffsmistypestateis(state1,state2,state3,state4);signalpr_state,nx_state:state;signaltemp:std_logic_vector(1downto0);beginprocess(rst,clk)beginif(rst='1')thenpr_state=state1;elsif(clk'eventandclk='1')thenoutp=temp;pr_state=nx_state;endif;endprocess;process(inp,pr_state)begincasepr_stateiswhenstate1=temp=00;if(inp='1')thennx_state=state2;elsenx_state=state1;endif;whenstate2=temp=01;if(inp='0')thennx_state=state3;elsenx_state=state4;endif;whenstate3=temp=10;if(inp='1')thennx_state=state4;elsenx_state=state3;endif;whenstate4=temp=11;if(inp='1')thennx_state=state1;elsenx_state=state2;endif;endcase;endprocess;endarch;3、通用奇偶校验发生器电路当输入矢量中'1'的个数分别为奇数和偶数时，所增加的输出位的值相应地为'1'和'0'，这样使得输出矢量中'1'的个数恒为偶数。1-------------------------------------------------2ENTITYparity_genIS3GENERIC(n:INTEGER:=7);4PORT(input:INBIT_VECTOR(n-1DOWNTO0);5output:OUTBIT_VECTOR(nDOWNTO0));6ENDparity_gen;7-------------------------------------------------8ARCHITECTUREparityOFparity_genIS9BEGIN10PROCESS(input)11VARIABLEtemp1:BIT;12VARIABLEtemp2:BIT_VECTOR(output'RANGE);13BEGIN14temp1:='0';15FORiINinput'RANGELOOP16temp1:=temp1XORinput(i);17temp2(i):=input(i);18ENDLOOP;19temp2(output'HIGH):=temp1;20output=temp2;21ENDPROCESS;22ENDparity;4、带7段数码显示的模100计数器，实现一个异步复位的模100累加计数器，此外它还可以将累加的BCD值转换成7段数码显示。1-------------------------------------------------2LIBRARYieee;3USEieee.std_logic_1164.all;4-------------------------------------------------5ENTITYcounterIS6PORT(clk,reset:INSTD_LOGIC;7digit1,digit2:OUTSTD_LOGIC_VECTOR(6DOWNTO0));8ENDcounter;9-------------------------------------------------10ARCHITECTUREcounterOFcounterIS11BEGIN12PROCESS(clk,reset)13VARIABLEtemp1:INTEGERRANGE0TO10;14VARIABLEtemp2:INTEGERRANGE0TO10;15BEGIN16--counter:-----17IF(reset='1')THEN18temp1:=0;19temp2:=0;20ELSIF(clk'EVENTANDclk='1')THEN21temp1:=temp1+1;22IF(temp1=10)THEN23temp1:=0;24temp2:=temp2+1;25IF(temp2=10)THEN26temp2:=0;27ENDIF;28ENDIF;29ENDIF;30---BCDtoSSDconversion:---31CASEtemp1IS32WHEN0=digit1=1111110;--7E33WHEN1=digit1=0110000;--3034WHEN2=digit1=1101101;--6D35WHEN3=digit1=1111001;--7936WHEN4=digit1=0110011;--3337WHEN5=digit1=1011011;--5B38WHEN6=digit1=1011111;--5F39WHEN7=digit1=1110000;--7040WHEN8=digit1=1111111;--7F41WHEN9=digit1=1111011;--7B42WHENOTHERS=NULL;43ENDCASE;44CASEtemp2IS45WHEN0=digit1=1111110;--7E46WHEN1=digit1=0110000;--3047WHEN2=digit1=1101101;--6D48WHEN3=digit1=1111001;--7949WHEN4=digit1=0110011;--3350WHEN5=digit1=1011011;--5B51WHEN6=digit1=1011111;--5F52WHEN7=digit1=1110000;--7053WHEN8=digit1=1111111;--7F54WHEN9=digit1=1111011;--7B55WHENOTHERS=NULL;56ENDCASE;57ENDPROCESS;58ENDcounter;5、使用loop语句实现对输入矢量中连续出现的零的个数进行统计1-------------------------------------------------2LIBRARYieee;3USEieee.std_logic_1164.all;4-------------------------------------------------5ENTITYLeadingZerosIS6PORT(data:INSTD_LOGIC_VECTOR(7DOWNTO0);7zeros:OUTINTEGERRANGE0TO8);8ENDLeadingZeros;9-------------------------------------------------10ARCHITECTUREbehaviorOFLeadingZerosIS11BEGIN12PROCESS(data)13VARIABLEcount:INTEGERRANGE0TO8;14BEGIN15count:=0;16FORiINdata'RANGELOOP17CASEdata(i)IS18WHEN'0'=count:=count+1;19WHENOTHERS=EXIT;20ENDCASE;21ENDLOOP;22zeros=count;23ENDPROCESS;24ENDbehavior;6、设计一个对时钟进行6分频的电路1-------------------------------------------------2LIBRARYieee;3USEieee.std_logic_1164.all;4-------------------------------------------------5ENTITYfreq_dividerIS6PORT(clk:INSTD_LOGIC;7out1,out2:BUFFERSTD_LOGIC);8EDNfreq_divider;9-------------------------------------------------10ARCHITECTUREexampleOFfreq_dividerIS11SIGNALcount1:INTEGERRANGE0TO7;12BEGIN13PROCESS(clk)14VARIABLEcount2:INTEGERRANGE0TO7;15BEGIN16IF(clk'EVENTANDclk='1')THEN17count1=count1+1;18count2:=count2+1;19IF(count1=?)THEN20out1=NOTout1;21count1=0;22ENDIF;23IF(coun2=?)THEN24out2=NOTout2;25count2:=0;26ENDIF27ENDIF;28ENDPROCESS;29ENDexample;Count1=2count2=37、信号发生器ENTITYsigISPORT(clk:INBIT;out1,out2:bufferBIT);ENDsig;ARCHITECTUREsigOFsigISTYPEstateIS(one,two,three,four);SIGNALpr_state1,nx_state1:state;SIGNALpr_state2,nx_state2:state;SIGNALpr_state3,nx_state3:state;SIGNALout3,out4,out5:BIT;BEGINPROCESS(clk)BEGINIF(clk'EVENTANDclk='1')THENpr_state1=nx_state1;ENDIF;ENDPROCESS;PROCESS(clk)BEGINIF(clk'EVENTANDclk='1')THENpr_state2=nx_state2;ENDIF;ENDPROCESS;PROCESS(clk)BEGINIF(clk'EVENTANDclk='0')THENpr_state3=nx_state3;ENDIF;ENDPROCESS;PROCESS(pr_state1)BEGINCASEpr_state1ISWHENone=out1='1';nx_state1=two;