FPGAmealy型状态机的设计

---------------------------------------------------------------------说明:mealy型状态机--文件:mealy1.vhd--作者:zhangqinguili--日期:2012/03/06--修改:--软件:AlteraQuartusII9.0--芯片:AlteraCycloneFPGA(EP1C3T144C8)-------------------------------------------------------------------LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmealy1ISPORT(CLK,RESET:INSTD_LOGIC;ina:INSTD_LOGIC_VECTOR(2DOWNTO0);outa:OUTSTD_LOGIC_VECTOR(3DOWNTO0));END;ARCHITECTUREbehavOFmealy1ISTYPEFSM_STIS(s0,s1,s2,s3);SIGNALcurrent_state:FSM_ST:=s0;BEGINREGCOM:PROCESS(CLK,RESET,current_state,ina)BEGINIFRESET='0'THENcurrent_state=S0;ELSIFRISING_EDGE(CLK)THEN--mealy型的特点是当状态current_state一发生变化，不用看时钟也马上发生变化CASEcurrent_stateISWHENs0=current_state=s1;WHENs1=IFina=000THENcurrent_state=s1;ELSIFina=110THENcurrent_state=s2;ENDIF;WHENs2=IFina=100THENcurrent_state=s2;ELSIFina=011THENcurrent_state=s1;ELSIFina/=100THENcurrent_state=s3;ENDIF;WHENs3=current_state=s0;ENDCASE;ENDIF;ENDPROCESSREGCOM;COM:PROCESS(current_state,ina)BEGINCASEcurrent_stateIS--输出状态WHENs0=IFina=101THENouta=0010;ELSIFina=111THENouta=1100;ENDIF;WHENs1=outa=1001;WHENs2=outa=1111;WHENs3=IFina=101THENouta=1101;ELSIFina=011THENouta=1110;ENDIF;ENDCASE;ENDPROCESSCOM;END;