FPGAUSB_BLASTER原理图与源程序

FPGAUSB_BLASTER原理图与源程序2008-02-2709:31:35|分类：技术文章|标签：|举报|字号大中小订阅原理图：CPLD源程序：LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;ENTITYjtag_logicISPORT(CLK:INSTD_LOGIC;--external24/25MHzoscillatornRXF:INSTD_LOGIC;--FT245BMnRXFnTXE:INSTD_LOGIC;--FT245BMnTXEB_TDO:INSTD_LOGIC;--JTAGinput:TDOoflastdeviceinchainnRD:OUTSTD_LOGIC;--FT245BMnRDWR:OUTSTD_LOGIC;--FT245BMWRB_TCK:BUFFERSTD_LOGIC;--JTAGoutput:TCKtochainB_TMS:BUFFERSTD_LOGIC;--JTAGoutput:TMStochainB_TDI:BUFFERSTD_LOGIC;--JTAGoutput:toTDIoffirstdeviceinchainD:INOUTSTD_LOGIC_VECTOR(7downto0)--FT245BMD[7..0]);ENDjtag_logic;ARCHITECTUREspecOFjtag_logicISTYPEstatesIS(wait_for_nRXF_low,set_nRD_low,keep_nRD_low,latch_data_from_host,set_nRD_high,bits_set_pins_from_data,bytes_set_bitcount,bytes_get_tdo_set_tdi,bytes_clock_high_and_shift,bytes_keep_clock_high,bytes_clock_finish,wait_for_nTXE_low,set_WR_high,output_enable,set_WR_low,output_disable);SIGNALcarry:STD_LOGIC;SIGNALdo_output:STD_LOGIC;SIGNALioshifter:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALbitcount:STD_LOGIC_VECTOR(8DOWNTO0);SIGNALstate,next_state:states;BEGIN--sm:PROCESS(nRXF,nTXE,state,D,bitcount,ioshifter,do_output)sm:PROCESS(nRXF,nTXE,state,bitcount,ioshifter,do_output)BEGINCASEstateIS--============================INPUTWHENwait_for_nRXF_low=IFnRXF='0'THENnext_state=set_nRD_low;ELSEnext_state=wait_for_nRXF_low;ENDIF;WHENset_nRD_low=next_state=keep_nRD_low;WHENkeep_nRD_low=next_state=latch_data_from_host;WHENlatch_data_from_host=next_state=set_nRD_high;WHENset_nRD_high=IFNOT(bitcount(8DOWNTO3)=000000)THENnext_state=bytes_get_tdo_set_tdi;ELSIFioshifter(7)='1'THENnext_state=bytes_set_bitcount;ELSEnext_state=bits_set_pins_from_data;ENDIF;WHENbytes_set_bitcount=next_state=wait_for_nRXF_low;--============================BITBANGINGWHENbits_set_pins_from_data=IFioshifter(6)='0'THENnext_state=wait_for_nRXF_low;--readnextbytefromhostELSEnext_state=wait_for_nTXE_low;--outputbytetohostENDIF;--============================BYTEOUTPUT(SHIFTOUT8BITS)WHENbytes_get_tdo_set_tdi=next_state=bytes_clock_high_and_shift;WHENbytes_clock_high_and_shift=next_state=bytes_keep_clock_high;WHENbytes_keep_clock_high=next_state=bytes_clock_finish;WHENbytes_clock_finish=IFNOT(bitcount(2DOWNTO0)=111)THENnext_state=bytes_get_tdo_set_tdi;--clocknextbitELSIFdo_output='1'THENnext_state=wait_for_nTXE_low;--outputbytetohostELSEnext_state=wait_for_nRXF_low;--readnextbytefromhostENDIF;--============================OUTPUTBYTETOHOSTWHENwait_for_nTXE_low=IFnTXE='0'THENnext_state=set_WR_high;ELSEnext_state=wait_for_nTXE_low;ENDIF;WHENset_WR_high=next_state=output_enable;WHENoutput_enable=next_state=set_WR_low;WHENset_WR_low=next_state=output_disable;WHENoutput_disable=next_state=wait_for_nRXF_low;--readnextbytefromhostWHENOTHERS=next_state=wait_for_nRXF_low;ENDCASE;ENDPROCESSsm;out_sm:PROCESS(CLK,state,ioshifter,B_TDO,bitcount,carry)BEGINIFCLK='1'ANDCLK'eventTHENIFstate=set_nRD_lowORstate=keep_nRD_lowORstate=latch_data_from_hostTHENnRD='0';ELSEnRD='1';ENDIF;IFstate=latch_data_from_hostTHENioshifter(7DOWNTO0)=D;ENDIF;IFstate=set_WR_highORstate=output_enableTHENWR='1';ELSEWR='0';ENDIF;IFstate=output_enableORstate=set_WR_lowTHEND=ioshifter(7DOWNTO0);ELSED=ZZZZZZZZ;ENDIF;IFstate=bits_set_pins_from_dataTHENB_TDI=ioshifter(4);B_TMS=ioshifter(1);B_TCK=ioshifter(0);ioshifter=0000001&B_TDO;ENDIF;IFstate=bytes_set_bitcountTHENbitcount=ioshifter(5DOWNTO0)&111;do_output=ioshifter(6);ENDIF;IFstate=bytes_get_tdo_set_tdiTHENcarry=B_TDO;B_TDI=ioshifter(0);bitcount=bitcount-1;ENDIF;IFstate=bytes_clock_high_and_shiftORstate=bytes_keep_clock_highTHENB_TCK='1';ENDIF;IFstate=bytes_clock_high_and_shiftTHENioshifter=carry&ioshifter(7DOWNTO1);ENDIF;IFstate=bytes_clock_finishTHENB_TCK='0';ENDIF;state=next_state;ENDIF;ENDPROCESSout_sm;ENDspec;