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实验一全加器设计仿真与下载四．实验内容及操作步骤1．设计一位全加器（1）完成电路的输入,以及对引脚的命名等（参考电路如图2－1）。（2）对一位全加器进行编译、仿真与下载。（3）点击File菜单的CreateDefaultSymbol项，创建缺省模块。2．利用一位全加器模块进行四位全加器的设计。（1）创建一个新的项目，新建文件。在新打开的图形编辑区双击左键，从EnterSymbol对话框中的用户目录（自创目录）下选择模块名。（2）连接线路，并进行编译（如图2－2）。（3）点击Assign菜单的Device项选择芯片。（4）管脚分配。（5）后编译，并进行下载。观察实验结果。实验二分频扫描与计数器设计4．四．实验内容与步骤1．设计一个分频电路已知cpld／fpga信号源脉冲频率为50M，试编写一分频程序，得到一周期为1秒（频率为1Hz）的脉冲频率，并将之形成include文件。(1)vhdl设计输入参考程序libraryieee;--调用库useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfpis-----实体说明（实体名需与文件名一致）port(inclk:instd_logic;------端口说明outputa:outstd_logic);endfp;architecturearch_fpoffpis------构造体说明signalfp:std_logic_vector(24downto0);------信号定义signalf:std_logic;beginprocess(inclk)------进程语句描述beginif(inclk'eventandinclk='1')then------将时钟分频至1Hziffp=24999999thenfp=0000000000000000000000000;f=notf;elsefp=fp+1;endif;endif;endprocess;outputa=f;endarch_fp;-------构造体结束（2）编译与仿真。要求：自己设计，试用VHDL编写一10分频程序，并创建include文件。2．12归1电路设计（1）创建一个新的项目。点击File→Project→ProjectName项；输入项目名称。（2）打开文本编辑窗口。点击File菜单下New项，选TextEditor项。（3）时钟源采用上面的分频电路所分得的1秒的时钟源。（4）用vhdl编写的例子libraryieee;-------调用库useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytwelveto1is-------实体描述port(finclk:instd_logic;--------端口说明outputa:outstd_logic_vector(6downto0);outputb:outstd_logic_vector(6downto0));endtwelveto1;architecturearch_twelveto1oftwelveto1is--------结构体描述signalsa:std_logic_vector(3downto0);signalsb:std_logic_vector(3downto0);signalf:std_logic;componentfp--------调用分频模块（分频模块需与此程序在同一文件夹下）port(inclk:instd_logic;outputa:outstd_logic);endcomponent;beginu1:fpportmap(inclk=finclk,outputa=f);process(f)--------进程语句描述beginif(rising_edge(f))then--------十二归一条件语句模块if(sa=2andsb=1)thensa=0001;sb=0000;elseifsa=9thensa=0000;sb=sb+1;elsesa=sa+1;endif;endif;endif;endprocess;withsaselect----sa表示个位outputa=0110000when0001,1101101when0010,1111001when0011,0110011when0100,1011011when0101,1011111when0110,1110000when0111,1111111when1000,1111011when1001,1110111when1010,0011111when1011,1001110when1100,0111101when1101,1001111when1110,1000111when1111,1111110whenothers;withsbselect----sb表示十位outputb=0110000when0001,1101101when0010,1111001when0011,0110011when0100,1011011when0101,1011111when0110,1110000when0111,1111111when1000,1111011when1001,1110111when1010,0011111when1011,1001110when1100,0111101when1101,1001111when1110,1000111when1111,1111110whenothers;endarch_twelveto1;实验三串行扫描显示电路设计1．四、实验内容及实验步骤1．串形扫描显示电路设计（1）用VHDL设计，示例如下：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytcxisport(inclk:instd_logic;outa:outstd_logic_vector(6downto0);---7位位宽，段选outb:outstd_logic_vector(3downto0));---4位位宽，位选endtcx;architecturearth_tcxoftcxissignalma:std_logic_vector(1downto0);signalmb:std_logic_vector(3downto0);---位选signalfp:std_logic_vector(23downto0);---段选signalf:std_logic;beginprocess(inclk)beginif(inclk'eventandinclk='1')theniffp=4999999thenfp=000000000000000000000000;f=notf;elsefp=fp+1;endif;endif;endprocess;process(f)---------扫描输出模块beginif(f'eventandf='1')thenma=ma+1;mb=mb+1;endif;endprocess;withmaselectoutb=0001when00,0010when01,0100when10,1000whenothers;withmbselectouta=0110000when0001,1101101when0010,1111001when0011,0110011when0100,1011011when0101,1011111when0110,1110000when0111,1111111when1000,1111011when1001,1110111when1010,0011111when1011,1001110when1100,0111101when1101,1001111when1110,1000111when1111,1111110whenothers;endarth_tcx;（2）编译。（3）分配管脚。（4）后编译。（5）启动CPLDDN下载软件进行下载。附：原程序扩展至8位libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytcxisport(inclk:instd_logic;outa:outstd_logic_vector(6downto0);outb:outstd_logic_vector(7downto0));endtcx;architecturearth_tcxoftcxissignalma:std_logic_vector(2downto0);signalmb:std_logic_vector(3downto0);signalfp:std_logic_vector(23downto0);signalf:std_logic;beginprocess(inclk)beginif(inclk'eventandinclk='1')theniffp=4999999thenfp=000000000000000000000000;f=notf;elsefp=fp+1;endif;endif;endprocess;process(f)-------扫描输出模块beginif(f'eventandf='1')thenma=ma+1;mb=mb+1;endif;endprocess;withmaselect------8位位选高电平有效outb=00000001when000,00000010when001,00000100when010,00001000when011,00010000when100,00100000when101,01000000when110,10000000when111;withmbselectouta=0110000when0001,1101101when0010,1111001when0011,0110011when0100,1011011when0101,1011111when0110,1110000when0111,1111111when1000,1111011when1001,1110111when1010,0011111when1011,1001110when1100,0111101when1101,1001111when1110,1000111when1111,1111110whenothers;endarth_tcx;实验四复杂数字钟电路设计（1）VHDL语言描述例子libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounterisport(inclk:instd_logic;outseg:outstd_logic_vector(6downto0);outbit:outstd_logic_vector(3downto0));endcounter;Architecturea_counterofcounterissignalma,mb,mc,md,mseg:std_logic_vector(3downto0);signallm,hm:std_logic_vector(12downto0);signalfpa,fpb:std_logic;signalst:std_logic_vector(1downto0);beginprocess(inclk)beginif(inclk'eventandinclk='1')theniflm=4999thenlm=0000000000000;fpa=notfpa;elselm=lm+1;endif;endif;endprocess;process(fpa)beginif(fpa'eventandfp