02-AD9361 Interface Spec v2.5

Page1of30AD9361InterfaceSpecificationAD9361InterfaceSpecificationADIConfidentialPage2of30TABLEOFCONTENTSRevisionHistory...............................................................................2GeneralDescription.........................................................................3ParallelDigitalInterface..................................................................4CMOSModeDataPathandClockSignals...............................4MaximumClockRatesandSignalBandwidths.......................5SinglePortHalfDuplexMode....................................................6SinglePortFullDuplexMode.....................................................9DualPortHalfDuplexMode....................................................12DualPortFullDuplexMode(FullPort).................................14DataBusIdleandTurnaroundPeriods...................................16DataPathTimingParameters...................................................16LVDSModeDataPathandClockSignals..............................17DataPathSignals........................................................................18MaximumClockRatesandSignalBandwidths.....................19DualPortFullDuplexMode(LVDS)......................................19DataPathFunctionalTiming...................................................20DataPathTimingParameters...................................................22AdjustableDataPathParameters.................................................23ConfigurationControlRegister...............................................23SerialPeripheralInterface(SPI)...................................................26SPIFunctionalLayer..................................................................26SPIDataTransferProtocol........................................................26TimingDiagrams.......................................................................28AdditionalInterfaceSignals..........................................................30CLOCK_OUT.............................................................................30CTRL_IN[3:0].............................................................................30CTRL_OUT[7:0]........................................................................30EN_AGC......................................................................................30GPO[3:0].....................................................................................30RESETB.......................................................................................30SYNC_IN.....................................................................................30REVISIONHISTORY11/2011—Rev.2.012/2011—Rev.2.1:Correctedwordingtoclarifyexplanations,addeddescriptionsfortwoSPIregisterbitsthatwerepreviouslyomitted.4/2012—Rev.2.2:Correcteddatapathtimingparameters,SPItimingtomatchthenumberslistedinthelatestdatasheet.6/2012—Rev.2.3:Correctedthedescriptionofusingregister0x000tosetuptheSPIbus,UpdatedtheLVDSdelayparametersforRX_FRAMEanddatarelativetotheDATA_CLKsignalbasedonstatisticaldata.7/2012—Rev.2.4:CorrectedtheLVDStimingparameterdiagraminFigure19toshowcorrectpolarityforFB_CLKandshowtHTX.TextwasaddedtoTable4toclarifythatsetupandholdtimingforTXdataarerelativetotheFB_CLKfallingedge.1/2013—Rev.2.5:CorrectedFigure14toremoveanyimpliedtimingrelationshipbetweenDATA_CLKandFB_CLK.ADIConfidentialAD9361InterfaceSpecificationPage3of30GENERALDESCRIPTIONThisdocumentdefinestheparalleldataportsandtheSerialPeripheralInterface(SPI)thatenablethetransferofdataandcontrol/statusinformationbetweentheAD9361andaBaseBandProcessor(BBP).Figure1illustratestheseinterfacesaswellasahigh-levelviewofhowtheAD9361andBBPareusedinabroadbandwirelesssystem.Thedatainterfaceoperatesinoneoftwomodes:standardCMOScompatiblemodeorLow-voltageDifferentialSignal(LVDS)compatiblemode.Eachinterfacepossessesuniquecharacteristicsdescribedinthefollowingsection.WhenCMOSmodeisused:•SingleendedCMOSlogiccompatibilityismaintained.•Eitheroneorbothdataportsmaybeutilized.Usingtwoportsallowsforhigherdatathroughput.•BothFrequency-DivisionDuplex(FDD)andTime-DivisionDuplex(TDD)operationaresupportedwithonedataportortwo.WhenLVDSmodeisused:•DataportsignalingisdifferentialLVDS,allowingupto12-inchPCBtraces/connectorinterconnectsbetweentheAD9361andtheBBP.•Onlythedataport(includingclockingandotherassociatedtimingsignals)isLVDScompatible.•BothFDDandTDDoperationaresupported.Figure1:AD9361InterfaceRFFRONTENDAD9361P1_D[11:0]P0_D[11:0]DATA_CLKFB_CLKRX_FRAMETX_FRAMETXNRXENABLEEN_AGCCTRL_OUTCTRL_INPLLCLK_OUTXTAL_NXTAL_PSPI_ENBSPI_CLKSPI_DISPI_DOBBPSYNC_IN1212222284AUX_DACTXRXTX_MONGPO128422AD9361InterfaceSpecificationADIConfidentialPage4of30PARALLELDIGITALINTERFACETheAD9361digitalinterfaceiscomprisedoftwoparalleldataportsandseveralclock,synchronization,andcontrolsignals.Thesesignalscanbeconfiguredassingle-endedCMOSsignalsorasLVDSsignalsforsystemsthatrequirehighspeed,lownoisedatatransfer.Thefollowingsectionsexplainthedetailsofthesignalsthatmakeupthedigitalinterfaceandtheirpropertieswhenconfiguredforeac