DS_K7R323682M中文资料

1Mx36&2Mx18&4Mx9QDRTMIIb2SRAM-1-Rev2.0Dec.2003K7R323682MK7R321882MK7R320982MDocumentTitle1Mx36-bit,2Mx18-bit,4Mx9-bitQDRTMIIb2SRAMTheattacheddatasheetsarepreparedandapprovedbySAMSUNGElectronics.SAMSUNGElectronicsCO.,LTD.reservetherighttochangethespecifications.SAMSUNGElectronicswillevaluateandreplytoyourrequestsandquestionsontheparametersofthisdevice.Ifyouhaveanyques-tions,pleasecontacttheSAMSUNGbranchofficenearyouroffice,callorcontactHeadquarters.RevisionHistoryRev.No.0.00.10.20.30.40.50.60.70.81.02.0RemarkAdvancePreliminaryPreliminaryPreliminaryPreliminaryPreliminaryPreliminaryPreliminaryPreliminaryFinalFinalHistory1.Initialdocument.1.PinnamechangefromDLLtoDoff.2.Vddqrangechangefrom1.5Vto1.5V~1.8V.3.UpdateJTAGtestconditions.4.ReservedpinforhighdensitynamechangefromNCtoVss/SA5.DeleteACtestconditionaboutClockInputtimingReferenceLevel6.Deleteclockdescriptiononpage2andaddHSTLI/Ocomment1.UpdatecurrentcharacteristicsinDCelectricalcharacteristics2.ChangeACtimingcharacteristics3.UpdateJTAGinstructioncodinganddiagrams1.Add4Mx9Organization.2.Add-FC25part(PartNumber,Idd,ACCharacteristics)3.AddACelectricalcharacteristics.4.ChangeACtimingcharacteristics.5.ChangeDCelectricalcharacteristics(ISB1)1.ChangethedataSetup/Holdtime.2.ChangetheAccessTime.(tCHQV,tCHQX,etc.)3.ChangetheClockCycleTime.(MAXvalueoftKHKH)4.ChangetheJTAGinstructioncoding.1.ChangetheBoundaryscanexitorder.2.ChangetheACtimingcharacteristics(-25,-20)3.CorrecttheOvershootandUndershoottimingdiagrams.1.ChangetheJTAGBlockdiagram1.CorrecttheJTAGIDregisterdefinition2.CorrecttheACtimingparameter(deletethetKHKHMaxvalue)3.ChangetheIsb1current.1.ChangetheMaximumClockcycletime.2.Correctthe165FBGApackageballsize.1.Finalspecrelease1.Deletethex8Org.PartDraftDateJune,302001Dec.52001July,29.2002Sep.6.2002Oct.7.2002Dec.16,2002Dec.26,2002Mar.20,2003April.4,2003Oct.31,2003Dec.1,20031Mx36&2Mx18&4Mx9QDRTMIIb2SRAM-2-Rev2.0Dec.2003K7R323682MK7R321882MK7R320982M1Mx36-bit,2Mx18-bit,4Mx9-bitQDRTMIIb2SRAMFEATURESFUNCTIONALBLOCKDIAGRAM•1.8V+0.1V/-0.1VPowerSupply.•DLLcircuitryforwideoutputdatavalidwindowandfuturefreguencyscaling.•I/OSupplyVoltage1.5V+0.1V/-0.1Vfor1.5VI/O,1.8V+0.1V/-0.1Vfor1.8VI/O.•Separateindependentreadandwritedataportswithconcurrentreadandwriteoperation•HSTLI/O•Fulldatacoherency,providingmostcurrentdata.•Synchronouspipelinereadwithselftimedearlywrite.•Registeredaddress,controlanddatainput/output.•DDR(DoubleDataRate)Interfaceonreadandwriteports.•Fixed2-bitburstforbothreadandwriteoperation.•Clock-stopsupportstoreducecurrent.•Twoinputclocks(KandK)foraccurateDDRtimingatclockrisingedgesonly.•Twoinputclocksforoutputdata(CandC)tominimizeclock-skewandflight-timemismatches.•Twoechoclocks(CQandCQ)toenhanceoutputdatatraceability.•Singleaddressbus.•Bytewrite(x9,x18,x36)function.•Sepatateread/writecontrolpin(RandW)•Simpledepthexpansionwithnodatacontention.•Programmableoutputimpenance.•JTAG1149.1compatibletestaccessport.•165FBGA(11x15ballarayFBGA)withbodysizeof15x17mmRADDRESSWCCD(Datain)ADDREGDATAREGCLKGENCTRLLOGIC1Mx36(2Mx18)MEMORYARRAYWRITEDRIVERKKBWX36(or18)4(or2)OrganizationPartNumberCycleTimeAccessTimeUnitX36K7R323682M-FC205.00.45nsK7R323682M-FC166.00.50nsX18K7R321882M-FC205.00.45nsK7R321882M-FC166.00.50nsX9K7R320982M-FC205.00.45nsK7R320982M-FC166.00.50nsSELECTOUTPUTCONTROLSENSEAMPSWRITE/READDECODEOUTPUTREGOUTPUTSELECTOUTPUTDRIVERNotes:1.Numbersin()areforx18device,x9devicealsothesamewithappropriateadjustmentsofdepthandwidth.721919(or20)36(or18)Q(DataOut)36(or18)36(or18)72(EchoClockout)CQ,CQQDRSRAMandQuadDataRatecompriseanewfamilyofproductsdevelopedbyCypress,Hitachi,IDT,Micron,NECandSamsungtechnology.(or20)(or36)(or36)1Mx36&2Mx18&4Mx9QDRTMIIb2SRAM-3-Rev2.0Dec.2003K7R323682MK7R321882MK7R320982MPINCONFIGURATIONS(TOPVIEW)K7R323682M(1Mx36)Notes:1.*CheckedNoConnect(NC)orVsspinsarereservedforhigherdensityaddress,i.e.3Afor72Mb,10Afor144Mband2Afor288Mb.2.BW0controlswritetoD0:D8,BW1controlswritetoD9:D17,BW2controlswritetoD18:D26andBW3controlswritetoD27:D35.1234567891011ACQVSS/SA*NC/SA*WBW2KBW1RSAVSS/SA*CQBQ27Q18D18SABW3KBW0SAD17Q17Q8CD27Q28D19VSSSASASAVSSD16Q7D8DD28D20Q19VSSVSSVSSVSSVSSQ16D15D7EQ29D29Q20VDDQVSSVSSVSSVDDQQ15D6Q6FQ30Q21D21VDDQVDDVSSVDDVDDQD14Q14Q5GD30D22Q22VDDQVDDVSSVDDVDDQQ13D13D5HDoffVREFVDDQVDDQVDDVSSVDDVDDQVDDQVREFZQJD31Q31D23VDDQVDDVSSVDDVDDQD12Q4D4KQ32D32Q23VDDQVDDVSSVDDVDDQQ12D3Q3LQ33Q24D24VDDQVSSVSSVSSVDDQD11Q11Q2MD33Q34D25VSSVSSVSSVSSVSSD10Q1D2ND34D26Q25VSSSASASAVSSQ10D9D1PQ35D35Q26SASACSASAQ9D0Q0RTDOTCKSASASACSASASATMSTDIPINNAMENotes:1.C,C,KorKcannotbesettoVREFvoltage.2.WhenZQpinisdirectlyconnectedtoVDDoutputimpedanceissettominimumvalueanditcannotbeconnectedtogroundorleftunconnected.3.Notconnectedtochippadinternally.SYMBOLPINNUMBERSDESCRIPTIONNOTEK,K6B,6AInputClockC,C6P,6RInputClockforOutputData1CQ,CQ11A,1AOutputEchoClockDoff1HDLLDisablewhenlowSA9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9RAddressInputsD0-3510P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N1C,1D,2E,1G,1J,2K,1M,1N,2PDataInputsQ0-3511P,10M,11L,11K,10J,11F,