CY7C4282V-25ASC中文资料

CY7C4282VCY7C4292V64K/128Kx9LowVoltageDeepSyncFIFOsw/Retransmit&DepthExpansionCypressSemiconductorCorporation•3901NorthFirstStreetSanJoseCA95134408-943-2600October18,1999Features•3.3Voperationforlowpowerconsumptionandeasyintegrationintolow-voltagesystemsHigh-speed,low-power,first-infirst-out(FIFO)memories64Kx9(CY7C4282V)128Kx9(CY7C4292V)0.35micronCMOSforoptimumspeed/powerHigh-speed,NearZeroLatency(TrueDual-PortedMemoryCell),100-MHzoperation(10nsread/writecycletimes)Lowpower—ICC=25mA—ISB=6mAFullyasynchronousandsimultaneousreadandwriteoperationEmpty,Full,andProgrammableAlmostEmptyandAl-mostFullstatusflagsRetransmitfunctionOutputEnable(OE)pinIndependentreadandwriteenablepinsSupportsfree-running50%dutycycleclockinputsWidthExpansionCapabilityDepthExpansionCapabilitythroughtoken-passingscheme(noexternallogicrequired)64-pin10x10STQFPPin-compatible3.3VsolutionforCY7C4282/92FunctionalDescriptionTheCY7C4282V/92Varehigh-speed,low-power,first-infirst-out(FIFO)memorieswithclockedreadandwriteinterfaces.Alldevicesare9bitswide.TheCY7C4282V/92Vcanbecas-cadedtoincreaseFIFOdepth.ProgrammablefeaturesincludeAlmostFull/AlmostEmptyflags.TheseFIFOsprovidesolutionsforawidevarietyofdatabufferingneeds,includinghigh-speeddataacquisition,multiprocessorinterfaces,videoandcommunicationsbuffering.TheseFIFOshave9-bitinputandoutputportsthatarecon-trolledbyseparateclockandenablesignals.Theinputportiscontrolledbyafree-runningclock(WCLK)andaWriteEnablepin(WEN).RetransmitandSynchronousAlmostFull/AlmostEmptyflagfeaturesareavailableonthesedevices.DepthexpansionispossibleusingtheCascadeInput(XI),Cas-cadeOutput(XO),andFirstLoad(FL)pins.TheXOpinisconnectedtotheXIpinofthenextdevice,andtheXOpinofthelastdeviceshouldbeconnectedtotheXIpinofthefirstdevice.TheFLpinofthefirstdeviceistiedtoVSSandtheFLpinofalltheremainingdevicesshouldbetiedtoVCCWhenWENisasserted,dataiswrittenintotheFIFOontherisingedgeoftheWCLKsignal.WhileWENisheldactive,dataiscontinuallywrittenintotheFIFOoneachcycle.Theoutputportiscontrolledinasimilarmannerbyafree-runningReadClock(RCLK)andaReadEnablepin(REN).Inaddition,theCY7C4282V/92VhaveanOutputEnablepin(OE).Thereadandwriteclocksmaybetiedtogetherforsingle-clockoperationorthetwoclocksmayberunindependentlyforasynchronousread/writeapplications.Clockfrequenciesupto67MHzareachievable.FFLogicBlockDiagram4282V–1THREE-STATEOUTPUTREGISTERREADCONTROLFLAGLOGICWRITECONTROLWRITEPOINTERREADPOINTERRESETLOGICINPUTREGISTERFLAGPROGRAMREGISTERD0−8RCLKQ0−8WENWCLKRSOEDualPortRAMArray64Kx9128Kx9RENEXPANSIONLOGICFL/RTXI/LDPAF/XOEFPAEPAF/XOCY7C4282VCY7C4292V2FunctionalDescription(continued)TheCY7C4282V/92Vprovidesfourstatuspins:Empty,Full,ProgrammableAlmostEmpty,andProgrammableAlmostFull.TheAlmostEmpty/AlmostFullflagsareprogrammabletosin-glewordgranularity.TheprogrammableflagsdefaulttoEmp-ty+7andFull−7.Theflagsaresynchronous,i.e.,theychangestaterelativetoeitherthereadclock(RCLK)orthewriteclock(WCLK).WhenenteringorexitingtheEmptyandAlmostEmptystates,theflagsareupdatedexclusivelybytheRCLK.TheflagsdenotingAlmostFull,andFullstatesareupdatedexclusivelybyWCLK.ThesynchronousflagarchitectureguaranteesthattheflagsmaintaintheirstatusforatleastonecycleAllconfigurationsarefabricatedusinganadvanced0.35µCMOStechnology.InputESDprotectionisgreaterthan2001V,andlatch-upispreventedbytheuseofguardrings.PinConfigurationSTQFPTopView123456789101112131415484746454443424140393837363534331764186319622061216022592358245725562655275428532952305131503249164282V–2CY7C4282VCY7C4292VWENRSD8D7D6N/CN/CN/CN/CN/CN/CD5N/CD2D4D3Q5Q4GNDQ3Q2VCCQ1Q0GNDN/CFFOEEFN/CGNDFL/RTWCLKXI/LDGNDN/CN/CN/CN/CN/CVCCN/CN/CQ7Q8N/CGNDQ6D1D0N/CN/CN/CVCCPAF/XOPAEN/CN/CN/CN/CN/CRCLKGNDRENSelectionGuide7C4282V/92V-107C4282V/92V-157C4282V/92V-25MaximumFrequency(MHz)10066.740MaximumAccessTime(ns)81015MinimumCycleTime(ns)101525MinimumDataorEnableSet-Up(ns)3.546MinimumDataorEnableHold(ns)001MaximumFlagDelay(ns)81015ActivePowerSupplyCurrent(ICC)(mA)Commercial252525Industrial30CY7C4282VCY7C4292VDensity64kx9128kx9Package64-pin10x10TQFP64-pin10x10TQFPCY7C4282VCY7C4292V3MaximumRatings(Abovewhichtheusefullifemaybeimpaired.Foruserguide-lines,nottested.)StorageTemperature.......................................−65°Cto+150°CAmbientTemperaturewithPowerApplied....................................................−55°Cto+125°CSupplyVoltagetoGroundPotential..........−0.5VtoVCC+0.5VDCVoltageAppliedtoOutputsinHighZState..............................................−0.5VtoVCC+0.5VDCInputVoltage.........................................−0.5VtoVCC+0.5VOutputCurrentintoOutputs(LOW).............................20mAStaticDischargeVoltage...........................................2001V(perMIL-STD-883,Method3015)Latch-UpCurrent.....................................................200mAPinDefinitionsSignalNameDescriptionI/ODescriptionD0−8DataInputsIDataInputsfor9-bitbus.Q0−8DataOutputsODataOutputsfor9-bitbus.WENWriteEnableITheonlywriteenablewhendeviceisconfiguredtohaveprogrammableflags.DataiswrittenonaLOW-to-HIGHtransitionofWCLKwhenWENis