CY7C4285-25ASC中文资料

32K/64Kx18DeepSyncFIFOsCY7C4275CY7C4285CypressSemiconductorCorporation•3901NorthFirstStreetSanJoseCA95134408-943-2600Document#:38-06008Rev.*ARevisedDecember26,2002285Features•High-speed,low-power,first-infirst-out(FIFO)memories32Kx18(CY7C4275)64Kx18(CY7C4285)0.5micronCMOSforoptimumspeed/powerHigh-speed100-MHzoperation(10-nsread/writecycletimes)Lowpower—ICC=50mA—ISB=2mAFullyasynchronousandsimultaneousreadandwriteoperationEmpty,Full,HalfFull,andprogrammableAlmostEmptyandAlmostFullstatusflagsTTLcompatibleRetransmitfunctionOutputEnable(OE)pinIndependentreadandwriteenablepinsCenterpowerandgroundpinsforreducednoiseSupportsfree-running50%dutycycleclockinputsWidthExpansionCapabilityDepthExpansionCapability68-pinPLCCand64-pin10x10TQFPPin-compatibledensityupgradetoCY7C42X5familiesPin-compatibledensityupgradetoIDT72205/15/25/35/45FunctionalDescriptionTheCY7C4275/85arehigh-speed,low-power,first-infirst-out(FIFO)memorieswithclockedreadandwriteinterfaces.Allare18bitswideandarepin/functionallycompatibletotheCY7C42X5SynchronousFIFOfamily.TheCY7C4275/85canbecascadedtoincreaseFIFOdepth.ProgrammablefeaturesincludeAlmostFull/AlmostEmptyflags.TheseFIFOsprovidesolutionsforawidevarietyofdatabufferingneeds,includinghigh-speeddataacquisition,multiprocessorinterfaces,andcommu-nicationsbuffering.TheseFIFOshave18-bitinputandoutputportsthatarecon-trolledbyseparateclockandenablesignals.Theinputportiscontrolledbyafree-runningclock(WCLK)andawriteenablepin(WEN).WhenWENisasserted,dataiswrittenintotheFIFOontherisingedgeoftheWCLKsignal.WhileWENisheldactive,dataiscontinu-allywrittenintotheFIFOoneachcycle.Theoutputportiscontrolledinasimilarmannerbyafree-runningreadclock(RCLK)andareadenablepin(REN).Inaddition,theCY7C4275/85haveanoutputenablepin(OE).Thereadandwriteclocksmaybetiedtogetherforsingle-clockoperationorthetwoclocksmayberunindependentlyforasynchronousread/writeapplications.Clockfrequenciesupto100MHzareachievable.RetransmitandSynchronousAlmostFull/AlmostEmptyflagfeaturesareavailableonthesedevices.Depthexpansionispossibleusingthecascadeinput(WXI,RXI),cascadeoutput(WXO,RXO),andFirstLoad(FL)pins.TheWXOandRXOpinsareconnectedtotheWXIandRXIpinsofthenextdevice,andtheWXOandRXOpinsofthelastdeviceshouldbeconnectedtotheWXIandRXIpinsofthefirstdevice.TheFLpinofthefirstdeviceistiedtoVSSandtheFLpinofalltheremainingdevic-esshouldbetiedtoVCC.Q0–174275–1THREE–STATEOUTPUTREGISTERREADCONTROLFLAGLOGICWRITECONTROLWRITEPOINTERREADPOINTERRESETLOGICEXPANSIONLOGICINPUTREGISTERFLAGPROGRAMREGISTERD0–17RENRCLKFFEFPAEWENWCLKRSFL/RTWXIOERAMARRAYPAFWXO/HFRXIRXOSMODELogicBlockDiagram32Kx1864Kx18CY7C4275CY7C4285Document#:38-06008Rev.*APage2of21FunctionalDescription(continued)TheCY7C4275/85providesfivestatuspins.Thesepinsaredecod-edtodetermineoneoffivestates:Empty,AlmostEmpty,HalfFull,AlmostFull,andFull(seeTable2).TheHalfFullflagsharestheWXOpin.Thisflagisvalidinthestand-aloneandwidth-expansionconfigurations.Inthedepthexpansion,thispinprovidestheexpansionout(WXO)informationthatisusedtosignalthenextFIFOwhenitwillbeactivated.TheEmptyandFullflagsaresynchronous,i.e.,theychangestaterelativetoeitherthereadclock(RCLK)orthewriteclock(WCLK).WhenenteringorexitingtheEmptystates,theflagisupdatedexclusivelybytheRCLK.TheflagdenotingFullstatesisupdatedexclusivelybyWCLK.Thesynchronousflagarchi-tectureguaranteesthattheflagswillremainvalidfromoneclockcycletothenext.TheAlmostEmpty/AlmostFullflagsbecomesynchronousiftheVCC/SMODEistiedtoVSS.Allconfigurationsarefabricatedusinganadvanced0.5µCMOStechnology.InputESDprotectionisgreaterthan2001V,andlatch-upispreventedbytheuseofguardrings.PinConfigurationsEF10111213141516171819202122232467TopView60595857565554535251504948313233343536373839404142435432168666564636261Q14Q13GNDQ12Q11VCCQ10Q9GNDQ8Q7VCCD14D13D12D11D10D9VCCD8GNDD7D6D5D427282930987647464544Q6Q5GNDQ4D3D2D1D02526VCC/SMODETQFPTopView4275–212345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916PLCCPAEFL/RTWCLKWENWXIVCCPAFRXIFFWXO/HFRXOQ0Q1GNDQ2Q3VCCQ15GNDQ16Q17VCCEFGNDVCCRSOELDRENRCLKGNDD17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0D15Q15GNDQ16Q17GNDVCCRSOELDRENRCLKGNDD17D16PAEWCLKWENWXIVCCPAFRXIFFWXO/HFRXOQ0Q1GNDQ2Q3Q14Q13GNDQ12Q11VCCQ10Q9GNDQ8Q7Q6Q5GNDQ4VCCVCC/SMODEFL/RT4275–3CY7C4275CY7C4285CY7C4275CY7C4285SelectionGuide7C4275/85-107C4275/85-157C4275/85-25MaximumFrequency(MHz)10066.740MaximumAccessTime(ns)81015MinimumCycleTime(ns)101525MinimumDataorEnableSet-Up(ns)346MinimumDataorEnableHold(ns)0.511MaximumFlagDelay(ns)81015ActivePowerSupplyCurrent(ICC1)(mA)Commercial505050Industrial55CY7C4275CY7C4285Density32Kx1864Kx18Packages64-pin10x10TQFP,68-pinPLCC64-pin10x10TQFP,68-pinPLCCCY7C4275CY7C4285Document#:38-06008Rev.*APage3of21PinDefinitionsSignalNameDescriptionI/OFunctionD0–17DataInputsIDatainputsforan18-bitbusQ0–17DataOutputsODataoutputsforan18-bitbusWENWriteEnableIEnablestheWCLKinputRENReadEnableIEnablestheRCLKinputWCLKWriteClockITherisingedgeclocksdataintotheFIFOwhenWENisLOWandtheFIFOisnotFull.WhenLDisasserted