ATTINY24A-PU中文资料

Features•HighPerformance,LowPowerAVR®8-BitMicrocontroller�AdvancedRISCArchitecture–120PowerfulInstructions–MostSingleClockCycleExecution–32x8GeneralPurposeWorkingRegisters–FullyStaticOperation�HighEndurance,Non-VolatileMemorySegments–2K/4KBytesofIn-System,Self-ProgrammableFlashProgramMemory�Endurance:10,000Write/EraseCycles–128/256BytesofIn-SystemProgrammableEEPROM�Endurance:100,000Write/EraseCycles–128/256BytesofInternalSRAM–Dataretention:20yearsat85°C/100yearsat25°C–ProgrammingLockforSelf-ProgrammingFlash&EEPROMDataSecurity�PeripheralFeatures–One8-BitandOne16-BitTimer/CounterwithTwoPWMChannels,Each–10-bitADC�8Single-EndedChannels�12DifferentialADCChannelPairswithProgrammableGain(1x/20x)–ProgrammableWatchdogTimerwithSeparateOn-chipOscillator–On-ChipAnalogComparator–UniversalSerialInterface�SpecialMicrocontrollerFeatures–debugWIREOn-chipDebugSystem–In-SystemProgrammableviaSPIPort–InternalandExternalInterruptSources�PinChangeInterrupton12Pins–LowPowerIdle,ADCNoiseReduction,StandbyandPower-DownModes–EnhancedPower-onResetCircuit–ProgrammableBrown-OutDetectionCircuitwithSoftwareDisableFunction–InternalCalibratedOscillator–On-ChipTemperatureSensor�I/OandPackages–Availablein20-PinQFN/MLF&14-PinSOICandPDIP–TwelveProgrammableI/OLines�OperatingVoltage:–1.8–5.5V�SpeedGrade:–0–4MHz@1.8–5.5V–0–10MHz@2.7–5.5V–0–20MHz@4.5–5.5V�IndustrialTemperatureRange:-40°Cto+85°C�LowPowerConsumption–ActiveMode:�210µAat1.8Vand1MHz–IdleMode:�33µAat1.8Vand1MHz–Power-DownMode:�0.1µAat1.8Vand25°C8-bitMicrocontrollerwith2K/4KBytesIn-SystemProgrammableFlashATtiny24A(Preliminary)ATtiny44ASummaryRev.8183AS–AVR–12/0828183AS–AVR–12/08ATtiny24A/44A1.PinConfigurationsFigure1-1.PinoutofATtiny24A/44A1.1PinDescriptions1.1.1VCCSupplyvoltage.1.1.2GNDGround.1.1.3PortB(PB3...PB0)PortBisa4-bitbi-directionalI/Oportwithinternalpull-upresistors(selectedforeachbit).ThePortBoutputbuffershavesymmetricaldrivecharacteristicswithbothhighsinkandsourcecapabilityexceptPB3whichhastheRESETcapability.TousepinPB3asanI/Opin,insteadofRESETpin,program(‘0’)RSTDISBLfuse.Asinputs,PortBpinsthatareexternallypulledlowwillsourcecurrentifthepull-upresistorsareactivated.ThePortBpinsaretri-statedwhenaresetconditionbecomesactive,eveniftheclockisnotrunning.1234567141312111098VCC(PCINT8/XTAL1/CLKI)PB0(PCINT9/XTAL2)PB1(PCINT11/RESET/dW)PB3(PCINT10/INT0/OC0A/CKOUT)PB2(PCINT7/ICP/OC0B/ADC7)PA7(PCINT6/OC1A/SDA/MOSI/DI/ADC6)PA6GNDPA0(ADC0/AREF/PCINT0)PA1(ADC1/AIN0/PCINT1)PA2(ADC2/AIN1/PCINT2)PA3(ADC3/T0/PCINT3)PA4(ADC4/USCK/SCL/T1/PCINT4)PA5(ADC5/DO/MISO/OC1B/PCINT5)PDIP/SOIC12345QFN/MLF15141312112019181716678910NOTEBottompadshouldbesolderedtoground.DNC:DoNotConnectDNCDNCGNDVCCDNCPA7(PCINT7/ICP/OC0B/ADC7)PB2(PCINT10/INT0/OC0A/CKOUT)PB3(PCINT11/RESET/dW)PB1(PCINT9/XTAL2)PB0(PCINT8/XTAL1/CLKI)PA5DNCDNCDNCPA6Pin16:PA6(PCINT6/OC1A/SDA/MOSI/DI/ADC6)Pin20:PA5(ADC5/DO/MISO/OC1B/PCINT5)(ADC4/USCK/SCL/T1/PCINT4)PA4(ADC3/T0/PCINT3)PA3(ADC2/AIN1/PCINT2)PA2(ADC1/AIN0/PCINT1)PA1(ADC0/AREF/PCINT0)PA038183AS–AVR–12/08ATtiny24A/44APortBalsoservesthefunctionsofvariousspecialfeaturesoftheATtiny24A/44AaslistedinSection10.2“AlternatePortFunctions”onpage57.1.1.4RESETResetinput.Alowlevelonthispinforlongerthantheminimumpulselengthwillgenerateareset,eveniftheclockisnotrunningandprovidedtheresetpinhasnotbeendisabled.Themin-imumpulselengthisgiveninTable20-4onpage176.Shorterpulsesarenotguaranteedtogenerateareset.Theresetpincanalsobeusedasa(weak)I/Opin.1.1.5PortA(PA7...PA0)PortAisa8-bitbi-directionalI/Oportwithinternalpull-upresistors(selectedforeachbit).ThePortAoutputbuffershavesymmetricaldrivecharacteristicswithbothhighsinkandsourcecapability.Asinputs,PortApinsthatareexternallypulledlowwillsourcecurrentifthepull-upresistorsareactivated.ThePortApinsaretri-statedwhenaresetconditionbecomesactive,eveniftheclockisnotrunning.PortAhasalternatefunctionsasanaloginputsfortheADC,analogcomparator,timer/counter,SPIandpinchangeinterruptasdescribedin“AlternatePortFunctions”onpage57.48183AS–AVR–12/08ATtiny24A/44A2.OverviewATtiny24A/44Aarelow-powerCMOS8-bitmicrocontrollersbasedontheAVRenhancedRISCarchitecture.Byexecutingpowerfulinstructionsinasingleclockcycle,theATtiny24A/44Aachievesthroughputsapproaching1MIPSperMHzallowingthesystemdesignertooptimizepowerconsumptionversusprocessingspeed.Figure2-1.BlockDiagramTheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.All32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowingtwoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclockcycle.Theresultingarchitectureismorecodeefficientwhileachievingthroughputsuptotentimesfasterthancon-ventionalCISCmicrocontrollers.WATCHDOGTIMERMCUCONTROLREGISTERTIMER/COUNTER0DATADIR.REG.PORTADATAREGISTERPORTAPROGRAMMINGLOGICTIMINGANDCONTROLMCUSTATUSREGISTERPORTADRIVERSPA7-PA0VCCGND+-ANALOGCOMPARATOR8-BITDATABUSADCISPINTERFACEINTERRUPTUNITEEPROMINTERNALOSCILLATOROSCILLATORSCALIBRATEDOSCILLATORINTERNALDATADIR.REG.PORTBDATAREGISTERPORTBPORTBDRIVERSPB3-PB0PROGRAMCOUNTERSTACKPOINTERPROGRAMFLASHSRAMGENERALPURPOSEREGIS