AT91SAM9G20-CU中文资料

NOTE:Thisisasummarydocument.ThecompletedocumentisavailableontheAtmelwebsiteat•IncorporatestheARM926EJ-S™ARM®Thumb®Processor–DSPInstructionExtensions,ARMJazelle®TechnologyforJava®Acceleration–32-KByteDataCache,32-KByteInstructionCache,WriteBuffer–CPUFrequency400MHz–MemoryManagementUnit–EmbeddedICE™,DebugCommunicationChannelSupport�AdditionalEmbeddedMemories–One64-KByteInternalROM,Single-cycleAccessatMaximumMatrixSpeed–Two16-KByteInternalSRAM,Single-cycleAccessatMaximumMatrixSpeed�ExternalBusInterface(EBI)–SupportsSDRAM,StaticMemory,ECC-enabledNANDFlashandCompactFlash®�USB2.0FullSpeed(12Mbitspersecond)DevicePort–On-chipTransceiver,2,432-byteConfigurableIntegratedDPRAM�USB2.0FullSpeed(12Mbitspersecond)HostandDoublePort–SingleorDualOn-chipTransceivers–IntegratedFIFOsandDedicatedDMAChannels�EthernetMAC10/100BaseT–MediaIndependentInterfaceorReducedMediaIndependentInterface–128-byteFIFOsandDedicatedDMAChannelsforReceiveandTransmit�ImageSensorInterface–ITU-RBT.601/656ExternalInterface,ProgrammableFrameCaptureRate–12-bitDataInterfaceforSupportofHighSensibilitySensors–SAVandEAVSynchronization,PreviewPathwithScaler,YCbCrFormat�BusMatrix–Six32-bit-layerMatrix–BootModeSelectOption,RemapCommand�Fully-featuredSystemController,including–ResetController,ShutdownController–Four32-bitBatteryBackupRegistersforaTotalof16Bytes–ClockGeneratorandPowerManagementController–AdvancedInterruptControllerandDebugUnit–PeriodicIntervalTimer,WatchdogTimerandReal-timeTimer�ResetController(RSTC)–BasedonaPower-onResetCell,ResetSourceIdentificationandResetOutputControl�ClockGenerator(CKGR)–Selectable32,768HzLow-powerOscillatororInternalLowPowerRCOscillatoronBatteryBackupPowerSupply,ProvidingaPermanentSlowClock–3to20MHzOn-chipOscillator,Oneupto800MHzPLLandOneupto100MHzPLL�PowerManagementController(PMC)–VerySlowClockOperatingMode,SoftwareProgrammablePowerOptimizationCapabilities–TwoProgrammableExternalClockSignals�AdvancedInterruptController(AIC)–IndividuallyMaskable,Eight-levelPriority,VectoredInterruptSources–ThreeExternalInterruptSourcesandOneFastInterruptSource,SpuriousInterruptProtected�DebugUnit(DBGU)–2-wireUARTandSupportforDebugCommunicationChannel,ProgrammableICEAccessPrevention–ModeforGeneralPurpose2-wireUARTSerialCommunicationAT91ARMThumbMicrocontrollersAT91SAM9G20Summary6384BS–ATARM–15-Dec-0826384BS–ATARM–15-Dec-08AT91SAM9G20Summary�PeriodicIntervalTimer(PIT)–20-bitIntervalTimerplus12-bitIntervalCounter�WatchdogTimer(WDT)–Key-protected,ProgrammableOnlyOnce,Windowed16-bitCounterRunningatSlowClock�Real-timeTimer(RTT)–32-bitFree-runningBackupCounterRunningatSlowClockwith16-bitPrescaler�One4-channel10-bitAnalog-to-DigitalConverter�Three32-bitParallelInput/OutputControllers(PIOA,PIOB,PIOC)–96ProgrammableI/OLinesMultiplexedwithuptoTwoPeripheralI/Os–InputChangeInterruptCapabilityonEachI/OLine–IndividuallyProgrammableOpen-drain,Pull-upResistorandSynchronousOutput–AllI/OLinesareSchmittTriggerInputs�PeripheralDMAControllerChannels(PDC)�OneTwo-slotMultiMediaCardInterface(MCI)–SDCard/SDIOandMultiMediaCard™Compliant–AutomaticProtocolControlandFastAutomaticDataTransferswithPDC�OneSynchronousSerialController(SSC)–IndependentClockandFrameSyncSignalsforEachReceiverandTransmitter–I²SAnalogInterfaceSupport,TimeDivisionMultiplexSupport–High-speedContinuousDataStreamCapabilitieswith32-bitDataTransfer�FourUniversalSynchronous/AsynchronousReceiverTransmitters(USART)–IndividualBaudRateGenerator,IrDA®InfraredModulation/Demodulation,ManchesterEncoding/Decoding–SupportforISO7816T0/T1SmartCard,HardwareHandshaking,RS485Support–FullModemSignalControlonUSART0�Two2-wireUARTs�TwoMaster/SlaveSerialPeripheralInterfaces(SPI)–8-to16-bitProgrammableDataLength,FourExternalPeripheralChipSelects–SynchronousCommunications�TwoThree-channel16-bitTimer/Counters(TC)–ThreeExternalClockInputs,TwoMulti-purposeI/OPinsperChannel–DoublePWMGeneration,Capture/WaveformMode,Up/DownCapability–High-DriveCapabilityonOutputsTIOA0,TIOA1,TIOA2�OneTwo-wireInterface(TWI)–CompatiblewithStandardTwo-wireSerialMemories–One,TwoorThreeBytesforSlaveAddress–SequentialRead/WriteOperations–Master,Multi-masterandSlaveModeOperation–BitRate:Upto400Kbits–GeneralCallSupportedinSlaveMode–ConnectiontoPeripheralDMAController(PDC)ChannelCapabilitiesOptimizesDataTransfersinMasterMode�IEEE®1149.1JTAGBoundaryScanonAllDigitalPins�RequiredPowerSupplies–0.9Vto1.1VforVDDBU,VDDCORE,VDDPLL–1.65to3.6VforVDDOSC–1.65Vto3.6VforVDDIOP(PeripheralI/Os)–3.0Vto3.6VforVDDUSB–3.0Vto3.6VVDDANA(Analog-to-digitalConverter)–Programmable1.65Vto1.95Vor3.0Vto3.6VforVDDIOM(MemoryI/Os)�Availableina217-ballLFBGARoHS-compliantPackage36384BS–ATARM–15-Dec-08AT91SAM9G20Summary1.DescriptionTheAT91SAM9G20isbasedontheintegrationofanARM926EJ-SprocessorwithfastROMandRAMmemoriesandawiderangeofperipherals.TheAT91SAM9G20embedsanEthernetMAC,oneUSBDevicePort,andaUSBHostcontrol-ler.Italsointegratesseveralstandardperipherals,suchastheUSART,SPI,TWI,TimerCounters,SynchronousSerialController,ADCandMultiMediaCardInterface.TheAT91SAM9G20isarchit