第7讲时序逻辑解析

©DigitalIntegratedCircuits2ndSequentialCircuits数字集成电路第七讲时序逻辑设计©DigitalIntegratedCircuits2ndSequentialCircuits时序逻辑两种存储机制:•正反馈存储•基于电荷的存储COMBINATIONALLOGICRegistersOutputsNextstateCLKQDCurrentStateInputs©DigitalIntegratedCircuits2ndSequentialCircuits命名规则Inourtext:锁存器alatchislevelsensitive寄存器aregisterisedge-triggeredTherearemanydifferentnamingconventions触发器Forinstance,manybookscalledge-triggeredelementsflip-flopsThisleadstoconfusionhowever©DigitalIntegratedCircuits2ndSequentialCircuits锁存器（Latch）和寄存器（Register）LatchstoresdatawhenclockislowDClkQClkDDClkQRegisterstoresdatawhenclockrisesClkDQQ©DigitalIntegratedCircuits2ndSequentialCircuits锁存器（Latches）©DigitalIntegratedCircuits2ndSequentialCircuitsLatch-BasedDesign•Nlatchistransparentwhenf=0•Platchistransparentwhenf=1NLatchLogicLogicPLatchf©DigitalIntegratedCircuits2ndSequentialCircuits正锁存器建立时间（D在时钟降为低电平之前需稳定的时间）时钟周期T时钟脉冲宽度保持时间（D在时钟降为低电平之后需稳定的时间）传播延迟时间（时钟上升沿到电平从D传输到Q所需要的时间）转换延迟时间（电平透明期间，D电平变传输到Q所需要的时间）TimingDefinitions(锁存器)©DigitalIntegratedCircuits2ndSequentialCircuitsTimingDefinitions(寄存器)tCLKtDtc-qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ建立时间保持时间传播延时©DigitalIntegratedCircuits2ndSequentialCircuitsMaximumClockFrequencyFF’sLOGICtp,combfAlso:tcdreg+tcdlogictholdtcd:contaminationdelay=minimumdelaytclk-Q+tp,comb+tsetup=T©DigitalIntegratedCircuits2ndSequentialCircuits7.2静态锁存器和寄存器7.2.1正反馈:双稳态原理Vo1Vi1Vo1Vi25Vo1Vo2Vi2Vi25Vo1ACBVi1=Vo2Vi2=Vo1电路有3个可能的工作点：A，B，C©DigitalIntegratedCircuits2ndSequentialCircuits亚稳态（Meta-Stability）亚稳态工作点稳态工作点©DigitalIntegratedCircuits2ndSequentialCircuits向静态锁存器写入一个值CLKCLKCLKDQDCLKCLKQConvertingintoaMUXForcingthestate(canimplementasNMOS-only)使用时钟作为一个去耦信号,用于区分透明和不透名状态DCLKQCLKQ要写入新值时，D的强度需要超过存储值，从而迫使新值进入该单元©DigitalIntegratedCircuits2ndSequentialCircuits7.2.2多路开关型锁存器Negativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLK10DQ0CLK1DQQClkQClkDQClkQClkD©DigitalIntegratedCircuits2ndSequentialCircuits多路开关型锁存器－传输门构成CLKCLKCLKDQ尺寸？功率？©DigitalIntegratedCircuits2ndSequentialCircuits多路开关型正锁存器－NMOS传输管构成CLKCLKCLKCLKQMQM电路图不重叠时钟仅用NMOS管会使送到第一个反相器输入的高电平降为VDD－VTn，会对噪声容限和开关性能有影响；另外对于第一个反相器，其最大输入电压为VDD－VTn，PMOS器件不能完全关闭，造成静态功耗。D©DigitalIntegratedCircuits2ndSequentialCircuits7.2.3主从式边沿触发寄存器TwooppositelatchestriggeronedgeAlsocalledmaster-slavelatchpair©DigitalIntegratedCircuits2ndSequentialCircuits主从式寄存器QMQDCLKT2I2T1I1I3T4I5T3I4I6基于锁存器对的上升沿触发器tpd-txtpd-inv01、工作原理2、时序特性：yx建立时间传播延时保持时间©DigitalIntegratedCircuits2ndSequentialCircuitsClk-QDelay©DigitalIntegratedCircuits2ndSequentialCircuitsSetupTime时钟在T2两端节点稳定到同一值之前就有效，造成不正确的值写入主锁存器。QMQDCLKT2I2T1I1I3T4I5T3I4I6yx©DigitalIntegratedCircuits2ndSequentialCircuits减小了时钟负载的主从式寄存器DQT1I1CLKCLKT2CLKCLKI2I3I4T1以及其驱动源必须比I2更强才能切换交叉耦合反相器的状态；反相器I1的输入必须超过它的开关阈值以便能够产生翻转。当从级导通时，T2和I4可能共同影响I1－I2锁存器中的数据；DDDD1、工作原理2、有比？3、反向传导4、时间参数xyz©DigitalIntegratedCircuits2ndSequentialCircuits非理想时钟(b)OverlappingclockpairsCLKCLKAB(a)SchematicdiagramXDQCLKCLKCLKCLK问题：1）当时钟变为高电平时，D和Q之间有直接通路，造成输出端数据可以在时钟上升沿改变。Q值取决于输入D是在CLK下降沿之前还是之后达到X。2）由于正负时钟之间存在重叠，节点A被D和B同时驱动，造成不确定状态。©DigitalIntegratedCircuits2ndSequentialCircuits解决办法－伪静态两相位D寄存器123©DigitalIntegratedCircuits2ndSequentialCircuits7.2.5使用强信号直接写数据－静态SR触发器ForbiddenStateSSRQQQQRSQQ00Q101001010110RQNOR-basedset-resetForbiddenStateSSRQQQQRSQQ00Q101001010110RQForbiddenStateSSRQQQQRSQQ00Q101001010110RQ©DigitalIntegratedCircuits2ndSequentialCircuits交叉耦合的NANDSQRQ有比？无比？M1M2M3M4QM5SM6CLKM7RM8CLKVDDQAddedclock10©DigitalIntegratedCircuits2ndSequentialCircuitsSizingIssuesOutputvoltagedependenceontransistorwidthTransientresponse4.03.53.0W/L5and6(a)2.52.00.00.51.01.52.0Q(Volts)time(ns)(b)00.20.40.60.811.21.41.61.82012W=1mm3VoltsQSW=0.9mmW=0.8mmW=0.7mmW=0.6mmW=0.5mm©DigitalIntegratedCircuits2ndSequentialCircuits信号存储原理DCLKCLKQ动态(基于电荷)CLKCLKCLKDQ静态©DigitalIntegratedCircuits2ndSequentialCircuits只需要8个晶体管。如果采样开关只使用NMOS传输管，只需6个晶体管；建立时间是传输门的延时，对应于节点A采样D所需时间；保持时间近似为0（传输门在时钟边沿关断）；传输时间为两个反相器的延时加上传输门T2的延时；必须周期性的刷新；CLK和CLK同时为高或低，有一条从D到Q的直接通路，导致Q可能在下降沿时就变化。功耗：时间参数：动态电路缺陷：时钟重叠问题：7.3.1动态边沿触发寄存器©DigitalIntegratedCircuits2ndSequentialCircuits把动态锁存器变为伪静态锁存器DCLKCLKD©DigitalIntegratedCircuits2ndSequentialCircuits7.3.2C2MOS－时钟控制CMOS寄存器M1DQM3CLKM4M2CLKVDDCL1XCL2MasterStageM5M7CLKCLKM8M6VDDSlaveStage©DigitalIntegratedCircuits2ndSequentialCircuits(a)(0-0)overlapM1DQM4M200VDDXM5M8M6VDDM3M1DQM21VDDXM71M5M6VDD(b)(1-1)overlap对时钟重叠不敏感－C2MOS©DigitalIntegratedCircuits2ndSequentialCircuits基于C2MOS的双边沿触发寄存器©DigitalIntegratedCircuits2ndSequentialCircuitsOtherLatches/Registers:TSPCR7.3.3真单相钟控锁存器CLKInVDDCLKVDDInOutCLKVDDCLKVDDOutNegativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)CLKInVDDCLKVDDInOutCLKVDDCLKVDDOut©DigitalIntegratedCircuits2ndSequentialCircuitsIncludingLogicinTSPCCLKInCLKVDDVDDQPUNPDNCLKVDDQCLKVDDIn1In1In2In2ANDlatchExample:logicinsidethelatchCLKInCLKVDDVDDQPUNPDNCLKVDDQCLKVDDIn1In1In2In2ABAB©DigitalIntegratedCircuits2ndSequentialCircuitsTSPCRegisterCLKCLKDVDDM3M2M1CLKYVDDQQM9M8M7CLKXVDDM6M5M41、工作原理2、时间参数3、竞争问题©DigitalIntegratedCircuits2ndSequentialCircuits7.5优化时序电路的方法——流水线REGREGREGlogaCLKCLKCLKOutbR