北科自动化数电pp6

Slide1CHAPTER6FunctionsofCombinationalLogic6-1BasicAdders6-2ParallelBinaryAdders并行二进制加法器6-3Comparators比较器6-4Decoders译码器6-5Encoders编码器6-6CodeConverters代码转换器6-7Multiplexers(DataSelectors)数据选择器/多路复用（MUX）6-8Demultiplexers多路分用器/解双工器（DEMUX）6-9ParityGenerator/Checker奇偶校验器IntroductiontoSeveralMSICombinationalCircuits介绍几种常用的中规模组件Slide2Inthischapteryoushouldknow:•TheinternalfunctionalprincipleofeveryMSIchips(inbrief)•ThoseMSIchipsarecombinationalcircuit(thatmeanstheyarecomposedoflogicgates);youshouldlearnhowtousethem•FocusonthesetwoblocksnameddecoderanddataselectorwhichcanbeusedtoproducesomegivenlogicfunctionSlide36-1BasicAdders(implementing1-bitaddition)基本加法器6-1-1Half-Adder半加器6-1-2Full-Adder全加器6-1-3Fulladderfromtwohalf-addercircuitsSlide4Generalrulesofbinaryaddition：a.Produceacarrybitwheneverwehave2b.LSBaddition:withoutconsideringthecarrybit。c.Whenprocessingtheotherbits,weshouldacceptthreenumbers(twoinputbitsandacarrybit)d.Anytwobitswillproduceasumbitandaoutputcarrywhenbeadded.Half-adderFull-adderSlide56-1-1Half-Adder(半加器)Howcouldweimplementthisfunctionusinglogiccircuit?Ahalf-adderisacombinationallogiccircuitthataddtogethertwoone-bitvaluesandproducesasumandacarryoutput.Thehalfpartofthenamecomesfromthelackofacarryinput.Slide60+0=00+1=11+0=11+1=10ZeropluszeroequalszeroZeroplusoneequalsoneOnepluszeroequalsoneOneplusoneequalszerowithacarryofoneSimpleBinaryAdditionSlide7Afull-adderisacombinationallogiccircuitthataddstwoone-bitvaluesplusacarrybitandproducesasumandacarryoutput.Thefullpartofthenamecomesfromthecarryinputbit.6-1-2Full-Adder全加器Slide8anbncn-1sncn0000000110010100110110010101011100111111Truthtable11)()(nnnnnnnnnnncbabacbabasnnnnnnnnbacbabac1)(Slide9Sketchtheinternallogiccircuitoffull-adderaccordingtothebooleanexpression.Slide10Slide116-1-3Fulladderfromtwohalf-addercircuitsSlide126-2ParallelBinaryAdders(implementingmore-bitaddition)并行二进制加法器6-2-1Two-bitparallelbinaryadder6-2-2Four-bitparallelbinaryadderHowcouldan-bitparalleladderbeconstructed?An-bitadderrequiresn-1full-addersandonehalf-adder.Howcouldafull-adderbefunctionedasahalf-adder?Slide136-2-1Two-bitparallelbinaryadderUsingtwofull-adderstoimplementA2A1+B2B1Slide14thepinsofdouble-full-adderSN74LS183114SN74LS1831an1bn1cn-11cn1sn2cn-12cn2sn2an2bnUccGNDSlide156-2-2Four-bitparallelbinaryadder四位并行二进制加法器Slide16ripplecarry（串行进位）addershowing“worst-case”carrypropagationdelays.CascadingFull-Adders串行全加器Slide17Look-AheadCarryadder:超前进位加法器：Slide18Carrygeneration:CgCarrypropagation:CpSlide19iiiiiniiiioutoutininoutinpgoutCBABACCCCBABACCCCC)()(1000000P191fourfull-addersoutputequation.Slide204位超前进位加法器74LS283内部结构Slide21Slide22Anotherapplicationofadder:AvotingsystemSlide236-3Comparators数值比较器Slide24Acomparatorsisacombinationallogiccircuitthatcomparestwobinaryinputvaluesandproducesresultsthatspecifytherelativevalueofoneinputwithrespecttotheother.OutputsofsomecomparatorsspecifywhetherA=B,othersmayspecifyA=B,ABandAB.Wewillfocusonthesecondcomparators.BinaryComparators二进制比较器Slide25输入输出ABABA=BAB00010010011010011010FunctiondescriptionBABA”“ABBABA”“BABA”“1-BitComparatorSlide26&&1ABABABA=BABABABA=BLogicdiagramLogicsymbolBABA”“ABBABA”“BABA”“Slide27Comparingprinciple：1.先从高位比起，高位大的数值一定大。2.若高位相等，则再比较低位数，最终结果由低位的比较结果决定。more-BitComparatorSlide28Truthtableforfour-bitcomparatora3b3100a3=b3a2=b2a1=b1a0=b0010a3=b3a2=b2a1=b1a0b0001a3=b3a2=b2a1=b1a0b0100a3=b3a2=b2a1b1001a3=b3a2=b2a1b1100a3=b3a2b2001a3=b3a2b2100a3b3001inputoutputa3b3a2b2a1b1a0b0LES(AB)(A=B)(AB)Slide29根据比较规则，可得到四位数值比较器逻辑式：A=B:BAE)ba)(ba)(ba)(ba(00112233AB:112233223333))(()(babababababaS00112233))()((babababaAB:SELSlide30Pindiagramandlogicsymbolforthe74HC854-bitmagnitudecomparator.Slide31A=B:BAEBAIbabababa))()()((00112233AB:112233223333))(()(babababababaSBAIbabababababababa))()()(())()((0011223300112233AB:SELSlide32例1：七位二进制数比较器。（采用两片85）“1”必接好（AB）L（AB）LABA=BABA1B1A0B0A3B3A2B2（A=B）L74LS85（AB）L（AB）LABA=BABA1B1A0B0A3B3A2B2（A=B）L74LS85(1)(2)a3a2a1a0a6a5a4Ab3b2b1b0b6b5b4B高位片低位片Slide336-5Encoders编码器Slide34EncodersAnencoderisacombinationallogiccircuitthataccepts2nbinaryinputsandproducesndataencodedoutputvalues.An8-to-3encoderhaseightinputlinesandthreeoutputlines.Whenoneofthedatainputsisactive,theoutputcodethatrepresentsthatvalueisgenerated.Slide3518-line-to-3-lineencoder（8线-3线编码器）2priorityencoder(优先编码器)3Decimal-to-BCDencoder（二－十进制编码器）Slide368-line-to-3-lineencoder设八个输入端为I1I8，八种状态，与之对应的输出设为F1、F2、F3，共三位二进制数。Slide37设计编码器的过程与设计一般的组合逻辑电路相同，首先要列出状态表（即真值表），然后写出逻辑表达式并进行化简，最后画出逻辑图。Slide38I1I2I3I4I5I6I7I8F3F2F10111111100010111111001110111110101110111101111110111100111110111011111110111011111110111Truthtable(active-lowinput)86421IIIIF8642IIII87432IIIIF87653IIIIFSlide39I1I2I3I4I5I6I7I8&&&F3F2F1Logicdiagram86421IIIIF8642IIII87432IIIIF87653IIIIFSlide40Priorityencoder(优先编码器)Logicdiagramof74LS148选通输入端选通输出端扩展端FunctiondescriptionSlide411XXXXXXXX11111011111111111010XXXXXXX0000100XXXXXX01001100XXXXX01101010…………………………………………00111111