usb布线要点

HighSpeedUSBPlatformDesignGuidelinesRev.1.0HighSpeedUSBPlatformDesignGuidelinesPage24/26/01REVISIONHISTORYRevisionRevisionHistoryDate0.9Preliminaryrelease.07/12/2000THISSPECIFICATION[DOCUMENT]ISPROVIDEDASISWITHNOWARRANTIESWHATSOEVER,INCLUDINGANYWARRANTYOFMERCHANTABILITY,NONINFRINGEMENT,FITNESSFORANYPARTICULARPURPOSE,ORANYWARRANTYOTHERWISEARISINGOUTOFANYPROPOSAL,SPECIFICATIONORSAMPLE.Inteldisclaimsallliability,includingliabilityforinfringementofanyproprietaryrights,relatingtouseofinformationinthisspecification.Nolicense,expressorimplied,byestoppelorotherwise,toanyintellectualpropertyrightsisgrantedherein.Intelassumesnoresponsibilityforanyerrors,whichmayappearinthisdocument.Intelmakesnocommitmenttoupdatetheinformationcontainedherein,andmaymakechangesatanytimewithoutnotice.Copyright©2000-01IntelCorporation.Allrightsreserved.*Third-partybrandsandnamesarethepropertyoftheirrespectiveowners.Otherproductandcorporatenamesmaybetrademarksofothercompaniesandareonlyforexplanationanttotheowners’benefit,withoutintenttoinfringe.HighSpeedUSBPlatformDesignGuidelinesPage34/26/01TableofContents:1Introduction________________________________________________________41.1Background___________________________________________________________________42Terminology________________________________________________________53LayoutGuidelines___________________________________________________53.1GeneralRoutingandPlacement___________________________________________________63.2HighSpeedUSBTraceSpacing___________________________________________________63.3HighSpeedUSBTermination____________________________________________________73.4HighSpeedUSBTraceLengthMatching____________________________________________73.5HighSpeedUSBTraceLengthGuidelines___________________________________________73.6PlaneSplits,VoidsandCut-Outs(Anti-Etch)________________________________________73.7LayerStacking_________________________________________________________________83.8ComponentPlacement___________________________________________________________84.1Stubs________________________________________________________________________94.2PoorRoutingTechniques________________________________________________________95EMI/ESDConsiderations_____________________________________________105.1EMI-CommonModeChokes___________________________________________________105.2ESD________________________________________________________________________126FrontPanelSolutions_______________________________________________126.1Cables______________________________________________________________________126.2Motherboard/PCBMatingConnector______________________________________________136.3FrontPanelConnectorCard_____________________________________________________147HighSpeedUSBDesignChecklist____________________________________17HighSpeedUSBPlatformDesignGuidelinesPage44/26/011IntroductionThisdocumentprovidesguidelinesforintegratingadiscretehighspeedUSBhostcontrollerontoafour-layerdesktopmotherboard.Thematerialcoveredcanbebrokenintothreemaincategories:Boarddesignguidelines,EMI/ESDguidelinesandfrontpanelUSBguidelines.Section1.1Backgroundprovidesanexplanationoftheroutingexperimentsandtestingperformedtovalidatethefeasibilityof480Megabitspersecondonanactualmotherboard.Section7containsadesignchecklistthatlistseachdesignrecommendationdescribedinthisdocument.HighspeedUSBoperationisdescribedintheUSB2.0Specification().BoarddesignguidelinesSpecificrequirementsconcerningroutingandplacementofthehostcontrollerrecommendedtraceseparation,terminationplacementrequirementsandoveralltracelengthguidelinesareprovided.Thesearefollowedbygeneralguidelinesconcerningplanesplits,layerstackupandcomponentplacement.SomeexamplesofcommonroutingmistakesarealsoincludedtoshowthedesignersomesuggestionsaboutwhattoavoidwhenroutingUSBsignals.EMI/ESDguidelinesEMIandESDsolutionsareprovidedbasedonactualmotherboardtesting.FrontpanelUSBguidelinesRecommendationsaremadeforfrontpanelcabling,motherboardmatingconnectorpin-out,routingconsiderationsanddaughterboarddesignguidelines.Theseguidelinesarebasedonsimulationsaswellasexperimentaltestingandmeasurement.1.1BackgroundAvarietyofplacementandroutingoptionswereinvestigatedusinghighspeedUSBtestsiliconplacedonafour-layermotherboard.Thistestingwasperformedtodeterminethefeasibilityofrouting480MegabitspersecondhighspeedUSBsignalsonarealmotherboardusingnormalcomponentplacement,densitiesandroutingconstraints.TheConstraintsTheroutingoftheProcessor/MemorybusandPCIbuseswithtoday’schipsetsdoesnotleavemanydegreesoffreedomforothermotherboardsignalsasshowninFigure1.Figure1MajorbusesoncurrentmotherboardsAhighspeedUSBhostcontrollerwillattachtothePCIbus,andsignalsmustberoutedtotheUSBconnectors.ThehighspeedUSBvalidationmotherboardexaminedtwocandidateplacementpositionsandtworoutingscenarios,asshowninFigure2.ThelongroutewaschosentousethepathcurrentlyusedbyMemoryProcessoranditspowersourceAudioNSLegacyIDE+FloppyAudioSerialParallelUSBMouseIN/OUT+LAN+KbdPCIAGPHighSpeedUSBPlatformDes