交通信号控制器的VHDL的设计

《EDA论文设计》EDA课程设计论文交通信号控制器的VHDL的设计学校：宁夏大学学院：物理电气信息学院班级：07级通信⑴班姓名：马磊学号：12007243815指导老师：马玉韬《EDA论文设计》摘要：本设计中选用目前应用较广泛的VHDL硬件电路描述语言,实现对路口交通灯系统的控制器的硬件电路描述,在Altera公司的EDA软件平台MAX+PLUSⅡ环境下通过了编译、仿真,并下载到CPLD器件上进行编程制作,实现了交通灯系统的控制过程。关键字：EDAVHDL控制器CPLD正文：一、设计目的：学习EDA的仿真软件maxplusII的使用方法，熟悉可编程逻辑器件的使用。通过制作来了解交通灯控制系统，交通灯控制系统主要是实现城市十字交叉路口红绿灯的控制二、设计原理：⑴交通灯从绿变红时，有5秒黄灯亮的间隔时间；⑵主干道上的绿灯时间为45秒，支干道的绿灯时间为25秒；在任意时间，显示每个状态到该状态结束所需的时间。支干道主干道图1路口交通管理示意图交通控制器工作原理表：交通灯状态MRMYMGBRBYBGA001100B010100C100001D100010《EDA论文设计》三、设计步骤及相应程序：（1）第一模块：交通灯控制（JTDKZ）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJTDKZISPORT(CLK,SM,SB:INSTD_LOGIC;MR,MY,MG,BR,BY,BG:OUTSTD_LOGIC);ENDENTITYJTDKZ;ARCHITECTUREARTOFJTDKZISTYPESTATE_TYPEIS(A,B,C,D);SIGNALSTATE:STATE_TYPE;BEGINCNT:PROCESS(CLK)ISVARIABLES:INTEGERRANGE0TO45;VARIABLECLR,EN:BIT;BEGINIF(CLK'EVENTANDCLK='1')THENIFCLR='0'THEn《EDA论文设计》S:=0;ELSIFEN='0'THENS:=S;ELSES:=S+1;ENDIF;CASESTATEISWHENA=MR='0';MY='0';MG='1';BR='1';BY='0';BG='0';IF(SBANDSM)='1'THENIFS=45THENSTATE=B;CLR:='0';EN:='0';ELSESTATE=A;CLR:='1';EN:='1';ENDIF;ELSIF(SBAND(NOTSM))='1'THENSTATE=B;CLR:='0';EN:='0';ELSESTATE=A;CLR:='1';EN:='1';ENDIF;WHENB=MR='0';MY='1';MG='0';BR='1';BY='0';BG='0';IFS=5THENSTATE=C;CLR:='0';EN:='0';ELSESTATE=B;CLR:='1';EN:='1';ENDIF;WHENC=MR='1';MY='0';MG='0';BR='0';BY='0';BG='1';IF(SMANDSB)='1'THENIFS=25THENSTATE=D;CLR:='0';EN:='0';ELSESTATE=C;CLR:='1';EN:='1';ENDIF;ELSIFSB='0'THENSTATE=D;CLR:='0';EN:='0';ELSESTATE=C;CLR:='1';EN:='1';ENDIF;WHEND=MR='1';MY='0';MG='0';BR='0';BY='1';BG='0';IFS=5THENSTATE=A;CLR:='0';EN:='0';ELSE《EDA论文设计》STATE=D;CLR:='1';EN:='1';ENDIF;ENDCASE;ENDIF;ENDPROCESSCNT;ENDARCHITECTUREART;（2）第二模块：45S计数器（CNT45）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT45SISPORT(SB,CLK,EN45:INSTD_LOGIC;DOUT45M,DOUT45B:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYCNT45S;ARCHITECTUREARTOFCNT45SISSIGNALCNT6B:STD_LOGIC_VECTOR(5DOWNTO0);BEGINPROCESS(SB,CLK,EN45)ISBEGINIFSB='0'THENCNT6B=CNT6B-CNT6B-1;ELSIF(CLK'EVENTANDCLK='1')THENIFEN45='1'THENCNT6B=CNT6B+1;ELSIFEN45='0'THENCNT6B=CNT6B-CNT6B-1;ENDIF;《EDA论文设计》ENDIF;ENDPROCESS;PROCESS(CNT6B)ISBEGINCASECNT6BISWHEN000000=DOUT45M=01000101;DOUT45B=01010000;WHEN000001=DOUT45M=01000100;DOUT45B=01001001;WHEN000010=DOUT45M=01000011;DOUT45B=01001000;WHEN000011=DOUT45M=01000010;DOUT45B=01000111;WHEN000100=DOUT45M=01000001;DOUT45B=01000110;WHEN000101=DOUT45M=01000000;DOUT45B=01000101;WHEN000110=DOUT45M=00111001;DOUT45B=01000100;WHEN000111=DOUT45M=00111000;DOUT45B=01000011;WHEN001000=DOUT45M=00110111;DOUT45B=01000010;WHEN001001=DOUT45M=00110110;DOUT45B=01000001;WHEN001010=DOUT45M=00110101;DOUT45B=01000000;WHEN001011=DOUT45M=00110100;DOUT45B=01101001;WHEN001100=DOUT45M=00110011;DOUT45B=00111000;WHEN001101=DOUT45M=00110010;DOUT45B=00110111;WHEN001110=DOUT45M=00110001;DOUT45B=00110110;WHEN001111=DOUT45M=00110000;DOUT45B=00110101;WHEN010000=DOUT45M=00101001;DOUT45B=00110100;WHEN010001=DOUT45M=00101000;DOUT45B=00110011;WHEN010010=DOUT45M=00100111;DOUT45B=00110010;WHEN010011=DOUT45M=00100110;DOUT45B=00110001;WHEN010100=DOUT45M=00100101;DOUT45B=00110000;WHEN010101=DOUT45M=00100100;DOUT45B=00101001;WHEN010110=DOUT45M=00100011;DOUT45B=00101000;WHEN100011=DOUT45M=00010000;DOUT45B=00010101;WHEN100100=DOUT45M=00001001;DOUT45B=00010100;WHEN100101=DOUT45M=00001000;DOUT45B=00010011;WHEN100110=DOUT45M=00000111;DOUT45B=00010010;WHEN100111=DOUT45M=00000110;DOUT45B=00010001;WHEN101000=DOUT45M=00000101;DOUT45B=00010000;WHEN101001=DOUT45M=00000100;DOUT45B=00001001;WHEN101010=DOUT45M=00000011;DOUT45B=00001000;WHEN101011=DOUT45M=00000010;DOUT45B=00000111;WHEN101100=DOUT45M=00000001;DOUT45B=00000110;WHENOTHERS=DOUT45M=00000000;DOUT45B=00000000;ENDCASE;ENDPROCESS;ENDARCHITECTUREART;仿真图《EDA论文设计》第三模块：5S计数器cnt5sLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT05SISPORT(CLK,EN05M,EN05B:INSTD_LOGIC;DOUT5:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYCNT05S;ARCHITECTUREARTOFCNT05SISSIGNALCNT3B:STD_LOGIC_VECTOR(2DOWNTO0);BEGINPROCESS(CLK,EN05M,EN05B)ISBEGINIF(CLK'EVENTANDCLK='1')THENIFEN05M='1'OREN05B='1'THENCNT3B=CNT3B+1;ELSECNT3B=000;ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT3B)ISBEGINCASECNT3BISWHEN000=DOUT5=00000101;WHEN001=DOUT5=00000100;WHEN010=DOUT5=00000011;WHEN011=DOUT5=00000010;WHEN100=DOUT5=00000001;WHENOTHERS=--DOUT5=00000000;ENDCASE;ENDPROCESS;《EDA论文设计》ENDARCHITECTUREART;⑶：第三模块：25S计时器（cnt25s）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT25SISPORT(SB,SM,CLK,EN25:INSTD_LOGIC;DOUT25M,DOUT25B:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYCNT25S;ARCHITECTUREARTOFCNT25SISSIGNALCNT5B:STD_LOGIC_VECTOR(4DOWNTO0);BEGINPROCESS(SB,SM,CLK,EN25)ISBEGINIFSB='0'ORSM='0'THENCNT5B=CNT5B-CNT5B-1;ELSIF(CLK'EVENTANDCLK='1')THENIFEN25='1'THENCNT5B=CNT5B+1;ELSIFEN25='0'THENCNT5B=CNT5B-CNT5B-1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT5B)ISBEGINCASECNT5BISWHEN00000=DOUT25B=00100101;DOUT25M=00110000;WHEN