A Proposal for a High-Performance Active Hardware

AProposalforaHigh-PerformanceActiveHardwareArchitectureTilmanWolfWUCS-99-08February15,1999AProposalforaHigh-PerformanceActiveHardwareArchitectureTilmanWolfDepartmentofComputerScienceWashingtonUniversityOneBrookingsDriveSt.Louis,MO63130ZROI#FFUFZXVWOHGXFebruary15,1999CurrentresearchinActiveNetworkingisfocusedondevelopingsoftwarearchitecturesanddefiningfunctionalityofExecutionEnvironments.Whileactivenetworksystemsshowsuperiorfunctionalitycomparedtotraditionalnetworks,theyonlyoperateatsubstantiallylowerlinkspeeds.ToincreasetheacceptanceofActiveNetworksinenvironmentswherelinkspeedsofseveralGb/sarecommon,weproposeahardwarearchitecturethatperformshigh-speedpackethandlingwhileprovidingthesameflexibilityasacommonsoftwaresystem.Thedesignexploitstheindependencebetweendatastreamsforparallelprocessing.Tomeasuretheimpactofdifferentdesigndecisionsontheperformanceofthesystem,wealsoproposeabenchmarkforActiveNetworkcomponents.ThisbenchmarkcanbeusedformanyActiveNetworkarchitecturesandcanhelptostandardizeperformanceresults.IntroductionActivenetworkingisanewapproachtogeneralizethecapabilityofnetworks.Byexecutingenduserspecifiedprogramswithinthenetwork,datapacketscanbehandledinacustomizedway.Thisallowstheeasyintroductionofnewnetworklayerprotocolsandapplicationswithoutchangingcomponentsofthenetworkinfrastructure.[1]Toimplementanactivenetwork,traditionalnetworkroutershavetobeaugmentedbythecapabilitytoexecutecustomizedcode,whichgoesbeyondthecommonheaderprocessingandsignaling.Currently,thisisachievedbyusingworkstationsasroutersintheexperimentalABONE[3].Theprocessingpowerofthegeneral-purposeworkstationCPUissharedamongtheoperatingsystem,theExecutionEnvironment,andtheprocessingofactivepackets.ThelimitedcomputationalpoweroftheworkstationrestrictsthedatatraffictoafewMb/s[6].Thisdatarateisseveralordersofmagnitudebelowthebandwidthofnewdatanetworks,whichoperateintheGb/srange.Fortheevolvingfieldofactivenetworksitiscrucialtobecompetitivewithrespecttotheend-to-endperformanceofcurrentnetworks.Thiscanbeachievedpartiallybyprovidingsuperiorfunctionality.However,thethroughputofanactivenetworksystemalsohastobeincreasedtotherangeofGb/s,otherwisetheacceptanceofactivenetworksforreal-worldapplicationsmightbelow.ThereisanapproachthatmakesuseofspecializedhardwareinformofanFPGA[4].However,thecomplexprogrammingandtheincompatibilitywithsoftwarethatisdevelopedforActiveExecutionEnvironments(EE)limitthewidespreaduse.Hereweproposeahardwarearchitectureforahigh-performanceActiveNetworkProcessingElement(ANPE)thatcanoperateatlinkspeedsintherangeofGb/s.ThisANPEcanbeusedonlinecardsofactiveroutersincombinationwithatraditionalhigh-performanceswitchingfabric.Also,theANPEcanbeusedonnetworkinterfacecardsofworkstationstoreducetheloadontheworkstationCPUcausedbyprocessingactivenetworktraffic.TheproposedhardwareisdesignedtofitonasingleASIC.Suchsystem-on-a-chiptechnologyallowsforthenecessaryhighperformanceofallcomponentstosupporthigh-bandwidthdatatraffic.ThedesignisgeneralenoughtobeusedfordifferentExecutionEnvironmenttomakeuseofthemostrecentdevelopmentsinActiveNetworksoftwaresystems.Inordertomeasuretheperformanceofthissystemandcompareittootheractivenetworkarchitectures,weproposeabenchmarkforactivenetworkcomponents.ThisbenchmarkdefinesseveraltypicalActiveApplications(AA)whichcoverawiderangeofcomputationalcomplexityandbandwidth,asuggestedtestenvironment,andmeasurementprocedures.Thefollowingsectiondescribesahardwarearchitecturethatmakesuseoftheparallelnatureofdatastreamstoachievehighperformance.Itsfunctionalityisillustrated,andconcurrencyandperformanceissuesaredescribed.TheActiveProcessingUnit(APU)whichprovidestheExecutionEnvironmentfortheprocessingoftheactivepacketisexplained.Thelastsectiondescribestheproposedbenchmark.ThecharacteristicsofActiveApplicationsaredescribedandusedtodetermineasetofbenchmarkapplicationsandatestenvironment.HardwareArchitectureOurproposalforanActiveNetworkProcessingElementinhardwareisbasedoncurrentdevelopmentsinASICtechnology.Itispossibletocombineflowclassification,routinglookup,activeprocessing,andschedulinginasingledesign.Weshowthatparallelprocessingcanbeusedtoachievehighperformancewhilekeepingconcurrencyissuesminimal.System-on-a-chiptechnologyThelevelsofintegrationandchipsizeshaveincreasedoverthelastyearstothepointwhereitispossibletocombineaprocessorandmemoryonasingleASIC.Thissystem-on-a-chiptechnologyprovidesaneasywaytobuildanANPEwithhighcomputationalpowerthatisspecializedonprocessingactivenetworktraffic.TheconventionalmeasureforthesizeofanASICisthenumberoflogicgatesortransistorsonachip.Figure1showssomerealworldexamplesobtainedfrompressreleasesofseveralASICmanufacturers.Itshowsthatthenumberoflogicgatesapproximatelydoubleseachyear.ThisestimateisalittlebitmoreoptimisticthanpredictedmyMoore’sLaw,whichexpectsthesizetodoubleevery18months.Withanincreasinglevelofintegration,notonlythesizeofASICsincrease,butalsotheclockspeedsatwhichtheyaredriven.Currentclockratescanrangeupto500MHz.Fig.1.DevelopmentinASICtechnology.Thegraphshowsthenumberoflogicgatesthatcanb