MB85RC16

FUJITSUSEMICONDUCTORDATASHEETCopyright©2011FUJITSUSEMICONDUCTORLIMITEDAllrightsreserved2011.6MemoryFRAM16K(2K×8)BitI2CMB85RC16■DESCRIPTIONTheMB85RC16isanFRAM(FerroelectricRandomAccessMemory)chipinaconfigurationof2,048words×8bits,usingtheferroelectricprocessandsilicongateCMOSprocesstechnologiesforformingthenonvolatilememorycells.UnlikeSRAM,theMB85RC16isabletoretaindatawithoutusingadatabackupbattery.ThememorycellsusedintheMB85RC16haveatleast1010Read/Writeoperationenduranceperbit,whichisasignificantimprovementoverthenumberofreadandwriteoperationssupportedbyothernonvolatilememoryproducts.TheMB85RC16canprovidewritinginonebyteunitsbecausethelongwritingtimeisnotrequiredunlikeFlashmemoryandE2PROM.Therefore,thewritingcompletionwaitingsequencelikeawritebusystateisnotrequired.■FEATURES•Bitconfiguration:2,048words×8bits�Operatingpowersupplyvoltage:2.7Vto3.6V�Operatingfrequency:1MHz(Max)�Two-wireserialinterface:Fullycontrollablebytwoports:serialclock(SCL)andserialdata(SDA).�Operatingtemperaturerange:−40°Cto+85°C�Dataretention:10years(+75°C)�Read/Writeendurance:1010times�Package:Plastic/SOP,8-pin(FPT-8P-M02)�Lowpowerconsumption:Operatingcurrent0.1mA(Max:@1MHz),Standbycurrent0.1μA(Typ)DS501-00001-2v0-EMB85RC162DS501-00001-2v0-E■PINASSIGNMENT■PINFUNCTIONALDESCRIPTIONSPinNumberPinNameFunctionalDescription1to3NCUnconnectedpinsLeaveitunconnected.4VSSGroundpin5SDASerialDataI/OpinThisisanI/Opinofserialdataforperformingbidirectionalcommunicationofmem-oryaddressandwritingorreadingdata.Itispossibletoconnectsomedevices.Itisanopendrainoutput,soapull-upresistanceisrequiredtobeconnectedtotheexternalcircuit.6SCLSerialClockpinThisisaclockinputpinforinput/outputtimingserialdata.Dataissampledontherisingedgeoftheclockandoutputonthefallingedge.7WPWriteProtectpinWhenWriteProtectpinis“H”level,writingoperationisdisabled.WhenWritePro-tectpinis“L”level,theentirememoryregioncanbeoverwritten.ReadingoperationisalwaysenabledregardlessoftheWriteProtectpinstate.ThewriteprotectpinisinternallypulleddowntoVSSpin,andthatisrecognizedas“L”level(thestatethatwritingisenabled)whenthepinistheopenstate.8VDDSupplyVoltagepinVSSSDANCVDDSCLNCNCWP87654321(TOPVIEW)(FPT-8P-M02)MB85RC16DS501-00001-2v0-E3■BLOCKDIAGRAM■I2C(Inter-IntegratedCircuit)TheMB85RC16hasthetwo-wireserialinterfaceandtheI2Cbus,andoperatesasaslavedevice.TheI2Cbusdefinescommunicationrolesof“master”and“slave”devices,withthemastersideholdingtheauthoritytoinitiatecontrol.Furthermore,aI2Cbusconnectionispossiblewhereasinglemasterdeviceisconnectedtomultipleslavedevicesinaparty-lineconfiguration.•I2CInterfaceSystemConfigurationExampleWPSDASCLRowDecoderMemoryAddressCounterFRAMArray2,048×8Serial/ParallelConverterColumnDecoder/SenseAmp/WriteAmpControlcircuitSCLVDDSDAI2CBusMasterI2CBusMB85RC16I2CBusOtherslavePull-upResistorsMB85RC164DS501-00001-2v0-E■I2CCOMMUNICATIONPROTOCOLTheI2Cbusprovidescommunicationbytwowiresonly,therefore,theSDAinputshouldchangewhileSCListhe“L”level.However,whenstartingandstoppingthecommunicationsequence,SDAisallowedtochangewhileSCListhe“H”level.�StartConditionTostartreadorwriteoperationsbytheI2Cbus,changetheSDAinputfromthe“H”leveltothe“L”levelwhiletheSCLinputisinthe“H”level.�StopConditionTostoptheI2Cbuscommunication,changetheSDAinputfromthe“L”leveltothe“H”levelwhiletheSCLinputisinthe“H”level.Inthereadingoperation,inputtingthestopconditionfinishesreadingandentersthestandbystate.Inthewritingoperation,inputtingthestopconditionfinishesinputtingtherewritedata.•StartCondition,StopConditionNote:TheFRAMdevicedoesnotneedtheprogrammingwaittime(tWC)afterissuingtheStopConditionduringthewriteoperation.SCLSDAStartStopMB85RC16DS501-00001-2v0-E5■ACKNOWLEDGE(ACK)IntheI2Cbus,serialdataincludingmemoryaddressormemoryinformationissentinunitsof8bits.Theacknowledgesignalindicatesthatevery8bitsofthedataissuccessfullysentandreceived.Thereceiversideusuallyoutputsthe“L”leveleverytimeonthe9thSCLclockafterevery8bitsaresuccessfullytrans-mitted.Onthetransmitterside,thebusistemporarilyreleasedonthis9thclocktoallowtheacknowledgesignaltobereceivedandchecked.Duringthisreleasedperiod,thereceiversidepullstheSDAlinedowntoindicatethatthecommunicationworkscorrectly.Ifthereceiversidereceivesthestopconditionbeforetransmittingtheacknowledge“L”level,thereadoperationendsandtheI2Cbusentersthestandbystate.Iftheacknowledge“L”levelisnotdetected,andtheStopconditionisnotsent,thebusremainsinthereleasedstatewithoutdoinganything.•Acknowledgetimingoverviewdiagram■MEMORYADDRESSSTRUCTURETheMB85RC16hasthememoryaddressbuffertostorethe11-bitinformationforthememoryaddress.Asforbytewrite,pagewriteandrandomreadcommands,thecomplete11-bitmemoryaddressisconfiguredbyinputtingthememoryupperaddress(3bits)andthememoryloweraddress(8bits),andsavingtothememoryaddressbufferandaccesstothememoryisperformed.Asforacurrentaddressreadcommand,thecomplete11-bitmemoryaddressisconfiguredbyinputtingthememoryupperaddress(3bits)andbythememoryaddresslower8-bitwhichhassavedinthememoryaddressbuffer,andsavingtothememoryaddressbufferandaccesstothememoryisperformed.SCL12389SDAStar