Arrow SoCKit Altera FPGA 开发板原理图

5544332211DDCCBBAASoCKit02.0102.05Transceiver802.0603.0103.02USBBlasterIIJTAGChain04.0103.0HSMC1PageJTAG151102.001.0TitleCoverPageSectionBlockDiagram1.012DesignIntroduction431.02657CycloneVEP5CSXFC6DF31BANK5&BANK6&BANK802.02BANK3&BANK402.0402.03BANK7Clock&GNDConfig04.0ExpansionPort05.0Memory05.01DDR3LSDRAMForFPGA05.02DDR3LSDRAMForHPS07.012008.0108.02LED&BUTTON&SWITCHForHPSVGAADV712309.02AudioSSM260309.0108.0LED&BUTTON&SWITCHForFPGA15PageVGA&Audio22232407.006.0TitleQSPIFLASHForFPGASectionQSPIFLASHForHPS06.0116Memory21706.021918LCD&Tempsensor&IRMLCD&Tempsensor&IRM09.0FPGA&HPSIO10.0USB&SDCARD&UART10.01UARTTOUSB&SDCARD10.02ULPIPHYUSB330011.0TSEPHYTSEPHYKSZ9021RN11.0112.0112.0LTCConnector&GSensorLTCConnector&GSensor13142521Page13.0TitleSectionSystemPower13.0113.0226279V&5V1.1V&1.2V3.3V&2.5V1.5V282913.0313.04HSMC_VCCIO13.0530PowerDecoupling02.0702.089103112TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.CoverPageBSoCKitBoardB131Tuesday,April30,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.CoverPageBSoCKitBoardB131Tuesday,April30,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.CoverPageBSoCKitBoardB131Tuesday,April30,20135544332211DDCCBBAATitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BlockDiagramBSoCKitBoardB231Tuesday,April30,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BlockDiagramBSoCKitBoardB231Tuesday,April30,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BlockDiagramBSoCKitBoardB231Tuesday,April30,20135544332211DDCCBBAADQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ22DQ21DQ20DQ23DQ26DQ25DQ24DQ27DQ30DQ29DQ28DQS_p0DQS_n0DQS_p1DQS_n1DQS_p2DQS_n2DQS_p3DQS_n3ODTDM0DM1DM3DM2DQ313.3V1.5V1.5VVGA_R5VGA_R7VGA_R6VGA_R0VGA_R4VGA_R3VGA_R2VGA_R1FPGA_DDR3_RZQ0USB_FULLUSB_EMPTYUSB_SCLUSB_SDAUSB_B2_CLKUSB_RESET_nUSB_OE_nUSB_RD_nUSB_WR_nFPGA_DDR3_A1FPGA_DDR3_A0FPGA_DDR3_A5FPGA_DDR3_A4FPGA_DDR3_A3FPGA_DDR3_A2FPGA_DDR3_A7FPGA_DDR3_A6FPGA_DDR3_CK_nFPGA_DDR3_CK_pFPGA_DDR3_BA2FPGA_DDR3_BA1FPGA_DDR3_BA0FPGA_DDR3_RAS_nFPGA_DDR3_CAS_nFPGA_DDR3_A9FPGA_DDR3_A8FPGA_DDR3_A11FPGA_DDR3_A10FPGA_DDR3_A13FPGA_DDR3_A12FPGA_DDR3_CS_nFPGA_DDR3_WE_nFPGA_DDR3_A14FPGA_DDR3_DQ22FPGA_DDR3_DQ19FPGA_DDR3_RESET_nFPGA_DDR3_DQS_n2FPGA_DDR3_DQ18FPGA_DDR3_DQ15FPGA_DDR3_DM1FPGA_DDR3_DQ12FPGA_DDR3_DQ13FPGA_DDR3_CKEFPGA_DDR3_DQ14FPGA_DDR3_DQ11FPGA_DDR3_DQS_n1FPGA_DDR3_DQS_p1FPGA_DDR3_DQ8FPGA_DDR3_DQ10FPGA_DDR3_DQ7FPGA_DDR3_DM0FPGA_DDR3_DQ4FPGA_DDR3_DQ5FPGA_DDR3_DQ6FPGA_DDR3_DQ3FPGA_DDR3_ODTFPGA_DDR3_DQS_n0FPGA_DDR3_DQS_p0FPGA_DDR3_DQ0FPGA_DDR3_DQ2FPGA_DDR3_DQ1FPGA_DDR3_DQ9FPGA_DDR3_DQ17FPGA_DDR3_DQ16FPGA_DDR3_DQS_p2FPGA_DDR3_DQ21FPGA_DDR3_DQ20FPGA_DDR3_DM2FPGA_DDR3_DQ23FPGA_DDR3_DQ25FPGA_DDR3_DQ24FPGA_DDR3_DQS_p3FPGA_DDR3_DQS_n3FPGA_DDR3_DQ27FPGA_DDR3_DQ30FPGA_DDR3_DQ29FPGA_DDR3_DQ28FPGA_DDR3_DM3FPGA_DDR3_DQ31FPGA_DDR3_DQ26USB_B2_DATA7USB_B2_DATA4USB_B2_DATA3USB_B2_DATA2USB_B2_DATA1USB_B2_DATA0USB_B2_DATA5USB_B2_DATA6GNDGNDGNDVGA_R[7..0]19VGA_VS19VGA_HS19VGA_SYNC_n19VGA_BLANK_n19TEMP_CS_n18TEMP_DIN18TEMP_DOUT18IRDA_RXD18TEMP_SCLK18FPGA_DDR3_DQ[31..0]14FPGA_DDR3_DQS_p[3..0]14FPGA_DDR3_DQS_n[3..0]14FPGA_DDR3_DM[3..0]14FPGA_DDR3_A[14..0]14FPGA_DDR3_CK_p14FPGA_DDR3_CK_n14FPGA_DDR3_CKE14FPGA_DDR3_CS_n14USB_SCL11USB_FULL11USB_EMPTY11USB_WR_n11USB_RD_n11USB_OE_n11USB_RESET_n11USB_B2_CLK11USB_SDA11USB_B2_DATA[7..0]11FPGA_DDR3_RESET_n14FPGA_DDR3_WE_n14FPGA_DDR3_RAS_n14FPGA_DDR3_CAS_n14FPGA_DDR3_ODT14FPGA_DDR3_BA[2..0]14TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BANK3&BANK4BSoCKitBoardB331Tuesday,April30,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissionofTerasic.Allrightsreserved.BANK3&BANK4BSoCKitBoardB331Tuesday,April30,2013TitleSizeDocumentNumberRevDate:SheetofCopyright(c)2013byTerasicTechnologiesInc.Taiwan.Nopartofthisschematicdesignmaybereproduced,duplicated,orusedwithoutthepriorwrittenpermissiono